merged with recent commits.
[gem5.git] / src / sim / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Nathan Binkert
30
31 Import('*')
32
33 SimObject('ClockedObject.py')
34 SimObject('TickedObject.py')
35 SimObject('Root.py')
36 SimObject('ClockDomain.py')
37 SimObject('VoltageDomain.py')
38 SimObject('System.py')
39 SimObject('DVFSHandler.py')
40 SimObject('SubSystem.py')
41
42 Source('arguments.cc')
43 Source('async.cc')
44 Source('core.cc')
45 Source('tags.cc')
46 Source('cxx_config.cc')
47 Source('cxx_manager.cc')
48 Source('cxx_config_ini.cc')
49 Source('debug.cc')
50 Source('py_interact.cc', skip_no_python=True)
51 Source('eventq.cc')
52 Source('global_event.cc')
53 Source('init.cc', skip_no_python=True)
54 Source('init_signals.cc')
55 Source('main.cc', main=True, skip_lib=True)
56 Source('root.cc')
57 Source('serialize.cc')
58 Source('drain.cc')
59 Source('sim_events.cc')
60 Source('sim_object.cc')
61 Source('sub_system.cc')
62 Source('ticked_object.cc')
63 Source('simulate.cc')
64 Source('stat_control.cc')
65 Source('stat_register.cc', skip_no_python=True)
66 Source('clock_domain.cc')
67 Source('voltage_domain.cc')
68 Source('system.cc')
69 Source('dvfs_handler.cc')
70
71 if env['TARGET_ISA'] != 'null':
72 SimObject('InstTracer.py')
73 SimObject('Process.py')
74 Source('faults.cc')
75 Source('process.cc')
76 Source('fd_entry.cc')
77 Source('pseudo_inst.cc')
78 Source('syscall_emul.cc')
79
80 DebugFlag('Checkpoint')
81 DebugFlag('Config')
82 DebugFlag('CxxConfig')
83 DebugFlag('Drain')
84 DebugFlag('Event')
85 DebugFlag('Fault')
86 DebugFlag('Flow')
87 DebugFlag('IPI')
88 DebugFlag('IPR')
89 DebugFlag('Interrupt')
90 DebugFlag('Loader')
91 DebugFlag('PseudoInst')
92 DebugFlag('Stack')
93 DebugFlag('SyscallVerbose')
94 DebugFlag('TimeSync')
95 DebugFlag('Thread')
96 DebugFlag('Timer')
97 DebugFlag('VtoPhys')
98 DebugFlag('WorkItems')
99 DebugFlag('ClockDomain')
100 DebugFlag('VoltageDomain')
101 DebugFlag('DVFS')