3 # Copyright (c) 2006 The Regents of The University of Michigan
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 # Authors: Nathan Binkert
33 SimObject('ClockedObject.py')
34 SimObject('TickedObject.py')
36 SimObject('ClockDomain.py')
37 SimObject('VoltageDomain.py')
38 SimObject('System.py')
39 SimObject('DVFSHandler.py')
40 SimObject('SubSystem.py')
42 Source('arguments.cc')
44 Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'])
47 Source('cxx_config.cc')
48 Source('cxx_manager.cc')
49 Source('cxx_config_ini.cc')
51 Source('py_interact.cc', skip_no_python=True)
53 Source('global_event.cc')
54 Source('init.cc', skip_no_python=True)
55 Source('init_signals.cc')
56 Source('main.cc', main=True, skip_lib=True)
58 Source('serialize.cc')
60 Source('sim_events.cc')
61 Source('sim_object.cc')
62 Source('sub_system.cc')
63 Source('ticked_object.cc')
65 Source('stat_control.cc')
66 Source('stat_register.cc', skip_no_python=True)
67 Source('clock_domain.cc')
68 Source('voltage_domain.cc')
69 Source('linear_solver.cc')
71 Source('dvfs_handler.cc')
72 Source('clocked_object.cc')
75 if env['TARGET_ISA'] != 'null':
76 SimObject('InstTracer.py')
77 SimObject('Process.py')
81 Source('pseudo_inst.cc')
82 Source('syscall_emul.cc')
83 Source('syscall_desc.cc')
85 if env['TARGET_ISA'] != 'x86':
86 Source('microcode_rom.cc')
88 DebugFlag('Checkpoint')
90 DebugFlag('CxxConfig')
97 DebugFlag('Interrupt')
99 DebugFlag('PseudoInst')
101 DebugFlag('SyscallBase')
102 DebugFlag('SyscallVerbose')
103 DebugFlag('TimeSync')
107 DebugFlag('WorkItems')
108 DebugFlag('ClockDomain')
109 DebugFlag('VoltageDomain')
112 CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose'])