src/sim/System.py

   1 # Copyright (c) 2017, 2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2011 Regents of the University of California
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39
  40 from m5.SimObject import *
  41 from m5.defines import buildEnv
  42 from m5.params import *
  43 from m5.proxy import *
  44
  45 from m5.objects.DVFSHandler import *
  46 from m5.objects.SimpleMemory import *
  47
  48 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
  49                                 'atomic_noncaching']
  50
  51 class System(SimObject):
  52     type = 'System'
  53     cxx_header = "sim/system.hh"
  54     system_port = MasterPort("System port")
  55
  56     cxx_exports = [
  57         PyBindMethod("getMemoryMode"),
  58         PyBindMethod("setMemoryMode"),
  59     ]
  60
  61     memories = VectorParam.AbstractMemory(Self.all,
  62                                           "All memories in the system")
  63     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
  64
  65     thermal_model = Param.ThermalModel(NULL, "Thermal model")
  66     thermal_components = VectorParam.SimObject([],
  67             "A collection of all thermal components in the system.")
  68
  69     # When reserving memory on the host, we have the option of
  70     # reserving swap space or not (by passing MAP_NORESERVE to
  71     # mmap). By enabling this flag, we accommodate cases where a large
  72     # (but sparse) memory is simulated.
  73     mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
  74                                           "without reserving swap")
  75
  76     # The memory ranges are to be populated when creating the system
  77     # such that these can be passed from the I/O subsystem through an
  78     # I/O bridge or cache
  79     mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
  80
  81     cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
  82
  83     redirect_paths = VectorParam.RedirectPath([], "Path redirections")
  84
  85     exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
  86                                     "encountering work item annotations.")
  87     work_item_id = Param.Int(-1, "specific work item id")
  88     num_work_ids = Param.Int(16, "Number of distinct work item types")
  89     work_begin_cpu_id_exit = Param.Int(-1,
  90         "work started on specific id, now exit simulation")
  91     work_begin_ckpt_count = Param.Counter(0,
  92         "create checkpoint when work items begin count value is reached")
  93     work_begin_exit_count = Param.Counter(0,
  94         "exit simulation when work items begin count value is reached")
  95     work_end_ckpt_count = Param.Counter(0,
  96         "create checkpoint when work items end count value is reached")
  97     work_end_exit_count = Param.Counter(0,
  98         "exit simulation when work items end count value is reached")
  99     work_cpus_ckpt_count = Param.Counter(0,
 100         "create checkpoint when active cpu count value is reached")
 101
 102     workload = Param.Workload(NULL, "Operating system kernel")
 103     init_param = Param.UInt64(0, "numerical value to pass into simulator")
 104     readfile = Param.String("", "file to read startup script from")
 105     symbolfile = Param.String("", "file to get the symbols from")
 106
 107     multi_thread = Param.Bool(False,
 108             "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
 109
 110     # Dynamic voltage and frequency handler for the system, disabled by default
 111     # Provide list of domains that need to be controlled by the handler
 112     dvfs_handler = DVFSHandler()
 113
 114     # SE mode doesn't use the ISA System subclasses, and so we need to set an
 115     # ISA specific value in this class directly.
 116     m5ops_base = Param.Addr(
 117         0xffff0000 if buildEnv['TARGET_ISA'] == 'x86' else 0,
 118         "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
 119         "to disable.")
 120
 121     if buildEnv['USE_KVM']:
 122         kvm_vm = Param.KvmVM(NULL, 'KVM VM (i.e., shared memory domain)')