mem: Minimize the use of MemObject.
[gem5.git] / src / sim / System.py
1 # Copyright (c) 2017 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # Copyright (c) 2011 Regents of the University of California
15 # All rights reserved.
16 #
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
27 #
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #
40 # Authors: Nathan Binkert
41 # Rick Strong
42
43 from m5.SimObject import *
44 from m5.defines import buildEnv
45 from m5.params import *
46 from m5.proxy import *
47
48 from m5.objects.DVFSHandler import *
49 from m5.objects.SimpleMemory import *
50
51 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
52 'atomic_noncaching']
53
54 class System(SimObject):
55 type = 'System'
56 cxx_header = "sim/system.hh"
57 system_port = MasterPort("System port")
58
59 cxx_exports = [
60 PyBindMethod("getMemoryMode"),
61 PyBindMethod("setMemoryMode"),
62 ]
63
64 memories = VectorParam.AbstractMemory(Self.all,
65 "All memories in the system")
66 mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
67
68 thermal_model = Param.ThermalModel(NULL, "Thermal model")
69 thermal_components = VectorParam.SimObject([],
70 "A collection of all thermal components in the system.")
71
72 # When reserving memory on the host, we have the option of
73 # reserving swap space or not (by passing MAP_NORESERVE to
74 # mmap). By enabling this flag, we accommodate cases where a large
75 # (but sparse) memory is simulated.
76 mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
77 "without reserving swap")
78
79 # The memory ranges are to be populated when creating the system
80 # such that these can be passed from the I/O subsystem through an
81 # I/O bridge or cache
82 mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
83
84 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
85
86 redirect_paths = VectorParam.RedirectPath([], "Path redirections")
87
88 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
89 "encountering work item annotations.")
90 work_item_id = Param.Int(-1, "specific work item id")
91 num_work_ids = Param.Int(16, "Number of distinct work item types")
92 work_begin_cpu_id_exit = Param.Int(-1,
93 "work started on specific id, now exit simulation")
94 work_begin_ckpt_count = Param.Counter(0,
95 "create checkpoint when work items begin count value is reached")
96 work_begin_exit_count = Param.Counter(0,
97 "exit simulation when work items begin count value is reached")
98 work_end_ckpt_count = Param.Counter(0,
99 "create checkpoint when work items end count value is reached")
100 work_end_exit_count = Param.Counter(0,
101 "exit simulation when work items end count value is reached")
102 work_cpus_ckpt_count = Param.Counter(0,
103 "create checkpoint when active cpu count value is reached")
104
105 init_param = Param.UInt64(0, "numerical value to pass into simulator")
106 boot_osflags = Param.String("a", "boot flags to pass to the kernel")
107 kernel = Param.String("", "file that contains the kernel code")
108 kernel_addr_check = Param.Bool(True,
109 "whether to address check on kernel (disable for baremetal)")
110 kernel_extras = VectorParam.String([],"Additional object files to load")
111 readfile = Param.String("", "file to read startup script from")
112 symbolfile = Param.String("", "file to get the symbols from")
113 load_addr_mask = Param.UInt64(0xffffffffffffffff,
114 "Address to mask loading binaries with, if 0, system "
115 "auto-calculates the mask to be the most restrictive, "
116 "otherwise it obeys a custom mask.")
117 load_offset = Param.UInt64(0, "Address to offset loading binaries with")
118
119 multi_thread = Param.Bool(False,
120 "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
121
122 # Dynamic voltage and frequency handler for the system, disabled by default
123 # Provide list of domains that need to be controlled by the handler
124 dvfs_handler = DVFSHandler()
125
126 if buildEnv['USE_KVM']:
127 kvm_vm = Param.KvmVM(NULL, 'KVM VM (i.e., shared memory domain)')