src/sim/clock_domain.cc

   1 /*
   2  * Copyright (c) 2013-2014, 2019 ARM Limited
   3  * Copyright (c) 2013 Cornell University
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Authors: Vasileios Spiliopoulos
  39  *          Akash Bagdia
  40  *          Andreas Hansson
  41  *          Christopher Torng
  42  *          Stephan Diestelhorst
  43  */
  44
  45 #include "sim/clock_domain.hh"
  46
  47 #include <algorithm>
  48 #include <functional>
  49
  50 #include "base/trace.hh"
  51 #include "debug/ClockDomain.hh"
  52 #include "params/ClockDomain.hh"
  53 #include "params/DerivedClockDomain.hh"
  54 #include "params/SrcClockDomain.hh"
  55 #include "sim/clocked_object.hh"
  56 #include "sim/voltage_domain.hh"
  57
  58 ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain &cd)
  59     : Stats::Group(&cd),
  60     ADD_STAT(clock, "Clock period in ticks")
  61 {
  62     // Expose the current clock period as a stat for observability in
  63     // the dumps
  64     clock.scalar(cd._clockPeriod);
  65 }
  66
  67 ClockDomain::ClockDomain(const Params *p, VoltageDomain *voltage_domain)
  68     : SimObject(p),
  69       _clockPeriod(0),
  70       _voltageDomain(voltage_domain),
  71       stats(*this)
  72 {
  73 }
  74
  75 double
  76 ClockDomain::voltage() const
  77 {
  78     return _voltageDomain->voltage();
  79 }
  80
  81 SrcClockDomain::SrcClockDomain(const Params *p) :
  82     ClockDomain(p, p->voltage_domain),
  83     freqOpPoints(p->clock),
  84     _domainID(p->domain_id),
  85     _perfLevel(p->init_perf_level)
  86 {
  87     VoltageDomain *vdom = p->voltage_domain;
  88
  89     fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
  90              "domain %d %s\n", _domainID, name());
  91
  92     fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
  93              "domain %d %s\n", _domainID, name());
  94
  95     fatal_if((vdom->numVoltages() > 1) &&
  96              (vdom->numVoltages() != freqOpPoints.size()),
  97              "DVFS: Number of frequency and voltage scaling points do "\
  98              "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
  99              freqOpPoints.size(), _domainID, name());
 100
 101     // Frequency (& voltage) points should be declared in descending order,
 102     // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
 103     fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
 104              "DVFS: Frequency operation points not in descending order for "\
 105              "domain with ID %d\n", _domainID);
 106
 107     fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
 108              "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
 109
 110     clockPeriod(freqOpPoints[_perfLevel]);
 111
 112     vdom->registerSrcClockDom(this);
 113 }
 114
 115 void
 116 SrcClockDomain::clockPeriod(Tick clock_period)
 117 {
 118     if (clock_period == 0) {
 119         fatal("%s has a clock period of zero\n", name());
 120     }
 121
 122     // Align all members to the current tick
 123     for (auto m = members.begin(); m != members.end(); ++m) {
 124         (*m)->updateClockPeriod();
 125     }
 126
 127     _clockPeriod = clock_period;
 128
 129     DPRINTF(ClockDomain,
 130             "Setting clock period to %d ticks for source clock %s\n",
 131             _clockPeriod, name());
 132
 133     // inform any derived clocks they need to updated their period
 134     for (auto c = children.begin(); c != children.end(); ++c) {
 135         (*c)->updateClockPeriod();
 136     }
 137 }
 138
 139 void
 140 SrcClockDomain::perfLevel(PerfLevel perf_level)
 141 {
 142     assert(validPerfLevel(perf_level));
 143
 144     if (perf_level == _perfLevel) {
 145         // Silently ignore identical overwrites
 146         return;
 147     }
 148
 149     DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
 150             "(id: %d) from  %d to %d\n", name(), domainID(), _perfLevel,
 151             perf_level);
 152
 153     _perfLevel = perf_level;
 154
 155     signalPerfLevelUpdate();
 156 }
 157
 158 void SrcClockDomain::signalPerfLevelUpdate()
 159 {
 160     // Signal the voltage domain that we have changed our perf level so that the
 161     // voltage domain can recompute its performance level
 162     voltageDomain()->sanitiseVoltages();
 163
 164     // Integrated switching of the actual clock value, too
 165     clockPeriod(clkPeriodAtPerfLevel());
 166 }
 167
 168 void
 169 SrcClockDomain::serialize(CheckpointOut &cp) const
 170 {
 171     SERIALIZE_SCALAR(_perfLevel);
 172     ClockDomain::serialize(cp);
 173 }
 174
 175 void
 176 SrcClockDomain::unserialize(CheckpointIn &cp)
 177 {
 178     ClockDomain::unserialize(cp);
 179     UNSERIALIZE_SCALAR(_perfLevel);
 180 }
 181
 182 void
 183 SrcClockDomain::startup()
 184 {
 185     // Perform proper clock update when all related components have been
 186     // created (i.e. after unserialization / object creation)
 187     signalPerfLevelUpdate();
 188 }
 189
 190 SrcClockDomain *
 191 SrcClockDomainParams::create()
 192 {
 193     return new SrcClockDomain(this);
 194 }
 195
 196 DerivedClockDomain::DerivedClockDomain(const Params *p) :
 197     ClockDomain(p, p->clk_domain->voltageDomain()),
 198     parent(*p->clk_domain),
 199     clockDivider(p->clk_divider)
 200 {
 201     // Ensure that clock divider setting works as frequency divider and never
 202     // work as frequency multiplier
 203     if (clockDivider < 1) {
 204        fatal("Clock divider param cannot be less than 1");
 205     }
 206
 207     // let the parent keep track of this derived domain so that it can
 208     // propagate changes
 209     parent.addDerivedDomain(this);
 210
 211     // update our clock period based on the parents clock
 212     updateClockPeriod();
 213 }
 214
 215 void
 216 DerivedClockDomain::updateClockPeriod()
 217 {
 218     // Align all members to the current tick
 219     for (auto m = members.begin(); m != members.end(); ++m) {
 220         (*m)->updateClockPeriod();
 221     }
 222
 223     // recalculate the clock period, relying on the fact that changes
 224     // propagate downwards in the tree
 225     _clockPeriod = parent.clockPeriod() * clockDivider;
 226
 227     DPRINTF(ClockDomain,
 228             "Setting clock period to %d ticks for derived clock %s\n",
 229             _clockPeriod, name());
 230
 231     // inform any derived clocks
 232     for (auto c = children.begin(); c != children.end(); ++c) {
 233         (*c)->updateClockPeriod();
 234     }
 235 }
 236
 237 DerivedClockDomain *
 238 DerivedClockDomainParams::create()
 239 {
 240     return new DerivedClockDomain(this);
 241 }