2 * Copyright (c) 2013-2014, 2019 ARM Limited
3 * Copyright (c) 2013 Cornell University
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include "sim/clock_domain.hh"
44 #include "base/trace.hh"
45 #include "debug/ClockDomain.hh"
46 #include "params/ClockDomain.hh"
47 #include "params/DerivedClockDomain.hh"
48 #include "params/SrcClockDomain.hh"
49 #include "sim/clocked_object.hh"
50 #include "sim/voltage_domain.hh"
52 ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain
&cd
)
54 ADD_STAT(clock
, "Clock period in ticks")
56 // Expose the current clock period as a stat for observability in
58 clock
.scalar(cd
._clockPeriod
);
61 ClockDomain::ClockDomain(const Params
&p
, VoltageDomain
*voltage_domain
)
64 _voltageDomain(voltage_domain
),
70 ClockDomain::voltage() const
72 return _voltageDomain
->voltage();
75 SrcClockDomain::SrcClockDomain(const Params
&p
) :
76 ClockDomain(p
, p
.voltage_domain
),
77 freqOpPoints(p
.clock
),
78 _domainID(p
.domain_id
),
79 _perfLevel(p
.init_perf_level
)
81 VoltageDomain
*vdom
= p
.voltage_domain
;
83 fatal_if(freqOpPoints
.empty(), "DVFS: Empty set of frequencies for "\
84 "domain %d %s\n", _domainID
, name());
86 fatal_if(!vdom
, "DVFS: Empty voltage domain specified for "\
87 "domain %d %s\n", _domainID
, name());
89 fatal_if((vdom
->numVoltages() > 1) &&
90 (vdom
->numVoltages() != freqOpPoints
.size()),
91 "DVFS: Number of frequency and voltage scaling points do "\
92 "not match: %d:%d ID: %d %s.\n", vdom
->numVoltages(),
93 freqOpPoints
.size(), _domainID
, name());
95 // Frequency (& voltage) points should be declared in descending order,
96 // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
97 fatal_if(!std::is_sorted(freqOpPoints
.begin(), freqOpPoints
.end()),
98 "DVFS: Frequency operation points not in descending order for "\
99 "domain with ID %d\n", _domainID
);
101 fatal_if(_perfLevel
>= freqOpPoints
.size(), "DVFS: Initial DVFS point %d "\
102 "is outside of list for Domain ID: %d\n", _perfLevel
, _domainID
);
104 clockPeriod(freqOpPoints
[_perfLevel
]);
106 vdom
->registerSrcClockDom(this);
110 SrcClockDomain::clockPeriod(Tick clock_period
)
112 if (clock_period
== 0) {
113 fatal("%s has a clock period of zero\n", name());
116 // Align all members to the current tick
117 for (auto m
= members
.begin(); m
!= members
.end(); ++m
) {
118 (*m
)->updateClockPeriod();
121 _clockPeriod
= clock_period
;
124 "Setting clock period to %d ticks for source clock %s\n",
125 _clockPeriod
, name());
127 // inform any derived clocks they need to updated their period
128 for (auto c
= children
.begin(); c
!= children
.end(); ++c
) {
129 (*c
)->updateClockPeriod();
134 SrcClockDomain::perfLevel(PerfLevel perf_level
)
136 assert(validPerfLevel(perf_level
));
138 if (perf_level
== _perfLevel
) {
139 // Silently ignore identical overwrites
143 DPRINTF(ClockDomain
, "DVFS: Switching performance level of domain %s "\
144 "(id: %d) from %d to %d\n", name(), domainID(), _perfLevel
,
147 _perfLevel
= perf_level
;
149 signalPerfLevelUpdate();
152 void SrcClockDomain::signalPerfLevelUpdate()
154 // Signal the voltage domain that we have changed our perf level so that the
155 // voltage domain can recompute its performance level
156 voltageDomain()->sanitiseVoltages();
158 // Integrated switching of the actual clock value, too
159 clockPeriod(clkPeriodAtPerfLevel());
163 SrcClockDomain::serialize(CheckpointOut
&cp
) const
165 SERIALIZE_SCALAR(_perfLevel
);
166 ClockDomain::serialize(cp
);
170 SrcClockDomain::unserialize(CheckpointIn
&cp
)
172 ClockDomain::unserialize(cp
);
173 UNSERIALIZE_SCALAR(_perfLevel
);
177 SrcClockDomain::startup()
179 // Perform proper clock update when all related components have been
180 // created (i.e. after unserialization / object creation)
181 signalPerfLevelUpdate();
184 DerivedClockDomain::DerivedClockDomain(const Params
&p
) :
185 ClockDomain(p
, p
.clk_domain
->voltageDomain()),
186 parent(*p
.clk_domain
),
187 clockDivider(p
.clk_divider
)
189 // Ensure that clock divider setting works as frequency divider and never
190 // work as frequency multiplier
191 if (clockDivider
< 1) {
192 fatal("Clock divider param cannot be less than 1");
195 // let the parent keep track of this derived domain so that it can
197 parent
.addDerivedDomain(this);
199 // update our clock period based on the parents clock
204 DerivedClockDomain::updateClockPeriod()
206 // Align all members to the current tick
207 for (auto m
= members
.begin(); m
!= members
.end(); ++m
) {
208 (*m
)->updateClockPeriod();
211 // recalculate the clock period, relying on the fact that changes
212 // propagate downwards in the tree
213 _clockPeriod
= parent
.clockPeriod() * clockDivider
;
216 "Setting clock period to %d ticks for derived clock %s\n",
217 _clockPeriod
, name());
219 // inform any derived clocks
220 for (auto c
= children
.begin(); c
!= children
.end(); ++c
) {
221 (*c
)->updateClockPeriod();