src/sim/clock_domain.cc

   1 /*
   2  * Copyright (c) 2013-2014, 2019 ARM Limited
   3  * Copyright (c) 2013 Cornell University
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include "sim/clock_domain.hh"
  40
  41 #include <algorithm>
  42 #include <functional>
  43
  44 #include "base/trace.hh"
  45 #include "debug/ClockDomain.hh"
  46 #include "params/ClockDomain.hh"
  47 #include "params/DerivedClockDomain.hh"
  48 #include "params/SrcClockDomain.hh"
  49 #include "sim/clocked_object.hh"
  50 #include "sim/voltage_domain.hh"
  51
  52 ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain &cd)
  53     : Stats::Group(&cd),
  54     ADD_STAT(clock, "Clock period in ticks")
  55 {
  56     // Expose the current clock period as a stat for observability in
  57     // the dumps
  58     clock.scalar(cd._clockPeriod);
  59 }
  60
  61 ClockDomain::ClockDomain(const Params &p, VoltageDomain *voltage_domain)
  62     : SimObject(p),
  63       _clockPeriod(0),
  64       _voltageDomain(voltage_domain),
  65       stats(*this)
  66 {
  67 }
  68
  69 double
  70 ClockDomain::voltage() const
  71 {
  72     return _voltageDomain->voltage();
  73 }
  74
  75 SrcClockDomain::SrcClockDomain(const Params &p) :
  76     ClockDomain(p, p.voltage_domain),
  77     freqOpPoints(p.clock),
  78     _domainID(p.domain_id),
  79     _perfLevel(p.init_perf_level)
  80 {
  81     VoltageDomain *vdom = p.voltage_domain;
  82
  83     fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
  84              "domain %d %s\n", _domainID, name());
  85
  86     fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
  87              "domain %d %s\n", _domainID, name());
  88
  89     fatal_if((vdom->numVoltages() > 1) &&
  90              (vdom->numVoltages() != freqOpPoints.size()),
  91              "DVFS: Number of frequency and voltage scaling points do "\
  92              "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
  93              freqOpPoints.size(), _domainID, name());
  94
  95     // Frequency (& voltage) points should be declared in descending order,
  96     // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
  97     fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
  98              "DVFS: Frequency operation points not in descending order for "\
  99              "domain with ID %d\n", _domainID);
 100
 101     fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
 102              "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
 103
 104     clockPeriod(freqOpPoints[_perfLevel]);
 105
 106     vdom->registerSrcClockDom(this);
 107 }
 108
 109 void
 110 SrcClockDomain::clockPeriod(Tick clock_period)
 111 {
 112     if (clock_period == 0) {
 113         fatal("%s has a clock period of zero\n", name());
 114     }
 115
 116     // Align all members to the current tick
 117     for (auto m = members.begin(); m != members.end(); ++m) {
 118         (*m)->updateClockPeriod();
 119     }
 120
 121     _clockPeriod = clock_period;
 122
 123     DPRINTF(ClockDomain,
 124             "Setting clock period to %d ticks for source clock %s\n",
 125             _clockPeriod, name());
 126
 127     // inform any derived clocks they need to updated their period
 128     for (auto c = children.begin(); c != children.end(); ++c) {
 129         (*c)->updateClockPeriod();
 130     }
 131 }
 132
 133 void
 134 SrcClockDomain::perfLevel(PerfLevel perf_level)
 135 {
 136     assert(validPerfLevel(perf_level));
 137
 138     if (perf_level == _perfLevel) {
 139         // Silently ignore identical overwrites
 140         return;
 141     }
 142
 143     DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
 144             "(id: %d) from  %d to %d\n", name(), domainID(), _perfLevel,
 145             perf_level);
 146
 147     _perfLevel = perf_level;
 148
 149     signalPerfLevelUpdate();
 150 }
 151
 152 void SrcClockDomain::signalPerfLevelUpdate()
 153 {
 154     // Signal the voltage domain that we have changed our perf level so that the
 155     // voltage domain can recompute its performance level
 156     voltageDomain()->sanitiseVoltages();
 157
 158     // Integrated switching of the actual clock value, too
 159     clockPeriod(clkPeriodAtPerfLevel());
 160 }
 161
 162 void
 163 SrcClockDomain::serialize(CheckpointOut &cp) const
 164 {
 165     SERIALIZE_SCALAR(_perfLevel);
 166     ClockDomain::serialize(cp);
 167 }
 168
 169 void
 170 SrcClockDomain::unserialize(CheckpointIn &cp)
 171 {
 172     ClockDomain::unserialize(cp);
 173     UNSERIALIZE_SCALAR(_perfLevel);
 174 }
 175
 176 void
 177 SrcClockDomain::startup()
 178 {
 179     // Perform proper clock update when all related components have been
 180     // created (i.e. after unserialization / object creation)
 181     signalPerfLevelUpdate();
 182 }
 183
 184 SrcClockDomain *
 185 SrcClockDomainParams::create() const
 186 {
 187     return new SrcClockDomain(*this);
 188 }
 189
 190 DerivedClockDomain::DerivedClockDomain(const Params &p) :
 191     ClockDomain(p, p.clk_domain->voltageDomain()),
 192     parent(*p.clk_domain),
 193     clockDivider(p.clk_divider)
 194 {
 195     // Ensure that clock divider setting works as frequency divider and never
 196     // work as frequency multiplier
 197     if (clockDivider < 1) {
 198        fatal("Clock divider param cannot be less than 1");
 199     }
 200
 201     // let the parent keep track of this derived domain so that it can
 202     // propagate changes
 203     parent.addDerivedDomain(this);
 204
 205     // update our clock period based on the parents clock
 206     updateClockPeriod();
 207 }
 208
 209 void
 210 DerivedClockDomain::updateClockPeriod()
 211 {
 212     // Align all members to the current tick
 213     for (auto m = members.begin(); m != members.end(); ++m) {
 214         (*m)->updateClockPeriod();
 215     }
 216
 217     // recalculate the clock period, relying on the fact that changes
 218     // propagate downwards in the tree
 219     _clockPeriod = parent.clockPeriod() * clockDivider;
 220
 221     DPRINTF(ClockDomain,
 222             "Setting clock period to %d ticks for derived clock %s\n",
 223             _clockPeriod, name());
 224
 225     // inform any derived clocks
 226     for (auto c = children.begin(); c != children.end(); ++c) {
 227         (*c)->updateClockPeriod();
 228     }
 229 }
 230
 231 DerivedClockDomain *
 232 DerivedClockDomainParams::create() const
 233 {
 234     return new DerivedClockDomain(*this);
 235 }