src/sim/clock_domain.cc

   1 /*
   2  * Copyright (c) 2013-2014, 2019 ARM Limited
   3  * Copyright (c) 2013 Cornell University
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include "sim/clock_domain.hh"
  40
  41 #include <algorithm>
  42 #include <functional>
  43
  44 #include "base/logging.hh"
  45 #include "base/trace.hh"
  46 #include "debug/ClockDomain.hh"
  47 #include "params/ClockDomain.hh"
  48 #include "params/DerivedClockDomain.hh"
  49 #include "params/SrcClockDomain.hh"
  50 #include "sim/clocked_object.hh"
  51 #include "sim/serialize.hh"
  52 #include "sim/voltage_domain.hh"
  53
  54 ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain &cd)
  55     : Stats::Group(&cd),
  56     ADD_STAT(clock, UNIT_TICK, "Clock period in ticks")
  57 {
  58     // Expose the current clock period as a stat for observability in
  59     // the dumps
  60     clock.scalar(cd._clockPeriod);
  61 }
  62
  63 ClockDomain::ClockDomain(const Params &p, VoltageDomain *voltage_domain)
  64     : SimObject(p),
  65       _clockPeriod(0),
  66       _voltageDomain(voltage_domain),
  67       stats(*this)
  68 {
  69 }
  70
  71 double
  72 ClockDomain::voltage() const
  73 {
  74     return _voltageDomain->voltage();
  75 }
  76
  77 SrcClockDomain::SrcClockDomain(const Params &p) :
  78     ClockDomain(p, p.voltage_domain),
  79     freqOpPoints(p.clock),
  80     _domainID(p.domain_id),
  81     _perfLevel(p.init_perf_level)
  82 {
  83     VoltageDomain *vdom = p.voltage_domain;
  84
  85     fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
  86              "domain %d %s\n", _domainID, name());
  87
  88     fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
  89              "domain %d %s\n", _domainID, name());
  90
  91     fatal_if((vdom->numVoltages() > 1) &&
  92              (vdom->numVoltages() != freqOpPoints.size()),
  93              "DVFS: Number of frequency and voltage scaling points do "\
  94              "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
  95              freqOpPoints.size(), _domainID, name());
  96
  97     // Frequency (& voltage) points should be declared in descending order,
  98     // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
  99     fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
 100              "DVFS: Frequency operation points not in descending order for "\
 101              "domain with ID %d\n", _domainID);
 102
 103     fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
 104              "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
 105
 106     clockPeriod(freqOpPoints[_perfLevel]);
 107
 108     vdom->registerSrcClockDom(this);
 109 }
 110
 111 void
 112 SrcClockDomain::clockPeriod(Tick clock_period)
 113 {
 114     if (clock_period == 0) {
 115         fatal("%s has a clock period of zero\n", name());
 116     }
 117
 118     // Align all members to the current tick
 119     for (auto m = members.begin(); m != members.end(); ++m) {
 120         (*m)->updateClockPeriod();
 121     }
 122
 123     _clockPeriod = clock_period;
 124
 125     DPRINTF(ClockDomain,
 126             "Setting clock period to %d ticks for source clock %s\n",
 127             _clockPeriod, name());
 128
 129     // inform any derived clocks they need to updated their period
 130     for (auto c = children.begin(); c != children.end(); ++c) {
 131         (*c)->updateClockPeriod();
 132     }
 133 }
 134
 135 void
 136 SrcClockDomain::perfLevel(PerfLevel perf_level)
 137 {
 138     assert(validPerfLevel(perf_level));
 139
 140     if (perf_level == _perfLevel) {
 141         // Silently ignore identical overwrites
 142         return;
 143     }
 144
 145     DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
 146             "(id: %d) from  %d to %d\n", name(), domainID(), _perfLevel,
 147             perf_level);
 148
 149     _perfLevel = perf_level;
 150
 151     signalPerfLevelUpdate();
 152 }
 153
 154 void SrcClockDomain::signalPerfLevelUpdate()
 155 {
 156     // Signal the voltage domain that we have changed our perf level so that the
 157     // voltage domain can recompute its performance level
 158     voltageDomain()->sanitiseVoltages();
 159
 160     // Integrated switching of the actual clock value, too
 161     clockPeriod(clkPeriodAtPerfLevel());
 162 }
 163
 164 void
 165 SrcClockDomain::serialize(CheckpointOut &cp) const
 166 {
 167     SERIALIZE_SCALAR(_perfLevel);
 168     ClockDomain::serialize(cp);
 169 }
 170
 171 void
 172 SrcClockDomain::unserialize(CheckpointIn &cp)
 173 {
 174     ClockDomain::unserialize(cp);
 175     UNSERIALIZE_SCALAR(_perfLevel);
 176 }
 177
 178 void
 179 SrcClockDomain::startup()
 180 {
 181     // Perform proper clock update when all related components have been
 182     // created (i.e. after unserialization / object creation)
 183     signalPerfLevelUpdate();
 184 }
 185
 186 DerivedClockDomain::DerivedClockDomain(const Params &p) :
 187     ClockDomain(p, p.clk_domain->voltageDomain()),
 188     parent(*p.clk_domain),
 189     clockDivider(p.clk_divider)
 190 {
 191     // Ensure that clock divider setting works as frequency divider and never
 192     // work as frequency multiplier
 193     if (clockDivider < 1) {
 194        fatal("Clock divider param cannot be less than 1");
 195     }
 196
 197     // let the parent keep track of this derived domain so that it can
 198     // propagate changes
 199     parent.addDerivedDomain(this);
 200
 201     // update our clock period based on the parents clock
 202     updateClockPeriod();
 203 }
 204
 205 void
 206 DerivedClockDomain::updateClockPeriod()
 207 {
 208     // Align all members to the current tick
 209     for (auto m = members.begin(); m != members.end(); ++m) {
 210         (*m)->updateClockPeriod();
 211     }
 212
 213     // recalculate the clock period, relying on the fact that changes
 214     // propagate downwards in the tree
 215     _clockPeriod = parent.clockPeriod() * clockDivider;
 216
 217     DPRINTF(ClockDomain,
 218             "Setting clock period to %d ticks for derived clock %s\n",
 219             _clockPeriod, name());
 220
 221     // inform any derived clocks
 222     for (auto c = children.begin(); c != children.end(); ++c) {
 223         (*c)->updateClockPeriod();
 224     }
 225 }