ruby: set: corrects csprintf() call introduced by 7d95b650c9b6
[gem5.git] / src / sim / core.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32 #ifndef __SIM_CORE_HH__
33 #define __SIM_CORE_HH__
34
35 /** @file This header provides some core simulator functionality such as time
36 * information, output directory and exit events
37 */
38
39 #include <string>
40
41 #include "base/types.hh"
42 #include "sim/eventq.hh"
43
44 /// The universal simulation clock.
45 inline Tick curTick() { return mainEventQueue.getCurTick(); }
46
47 const Tick retryTime = 1000;
48
49 /// These are variables that are set based on the simulator frequency
50 ///@{
51 namespace SimClock {
52 extern Tick Frequency; ///< The number of ticks that equal one second
53
54 namespace Float {
55
56 /** These variables equal the number of ticks in the unit of time they're
57 * named after in a double.
58 * @{
59 */
60 extern double s; ///< second
61 extern double ms; ///< millisecond
62 extern double us; ///< microsecond
63 extern double ns; ///< nanosecond
64 extern double ps; ///< picosecond
65 /** @} */
66
67 /** These variables the inverse of above. They're all < 1.
68 * @{
69 */
70 extern double Hz; ///< Hz
71 extern double kHz; ///< kHz
72 extern double MHz; ///< MHz
73 extern double GHZ; ///< GHz
74 /** @}*/
75 } // namespace Float
76
77 /** These variables equal the number of ticks in the unit of time they're
78 * named after in a 64 bit integer.
79 *
80 * @{
81 */
82 namespace Int {
83 extern Tick s; ///< second
84 extern Tick ms; ///< millisecond
85 extern Tick us; ///< microsecond
86 extern Tick ns; ///< nanosecond
87 extern Tick ps; ///< picosecond
88 /** @} */
89 } // namespace Int
90 } // namespace SimClock
91 /** @} */
92 void setClockFrequency(Tick ticksPerSecond);
93
94 void setOutputDir(const std::string &dir);
95
96 class Callback;
97 void registerExitCallback(Callback *callback);
98 void doExitCleanup();
99
100 #endif /* __SIM_CORE_HH__ */