src/sim/faults.cc

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "sim/faults.hh"
  42
  43 #include "arch/decoder.hh"
  44 #include "arch/locked_mem.hh"
  45 #include "base/logging.hh"
  46 #include "cpu/base.hh"
  47 #include "cpu/thread_context.hh"
  48 #include "debug/Fault.hh"
  49 #include "mem/page_table.hh"
  50 #include "sim/full_system.hh"
  51 #include "sim/process.hh"
  52
  53 void
  54 FaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  55 {
  56     panic_if(!FullSystem, "fault (%s) detected @ PC %s",
  57              name(), tc->pcState());
  58     DPRINTF(Fault, "Fault %s at PC: %s\n", name(), tc->pcState());
  59 }
  60
  61 void
  62 UnimpFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  63 {
  64     panic("Unimpfault: %s", panicStr.c_str());
  65 }
  66
  67 void
  68 SESyscallFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  69 {
  70     tc->syscall();
  71     // Move the PC forward since that doesn't happen automatically.
  72     TheISA::PCState pc = tc->pcState();
  73     inst->advancePC(pc);
  74     tc->pcState(pc);
  75 }
  76
  77 void
  78 ReExec::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  79 {
  80     tc->pcState(tc->pcState());
  81 }
  82
  83 void
  84 SyscallRetryFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  85 {
  86     tc->pcState(tc->pcState());
  87 }
  88
  89 void
  90 GenericPageTableFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
  91 {
  92     bool handled = false;
  93     if (!FullSystem) {
  94         Process *p = tc->getProcessPtr();
  95         handled = p->fixupFault(vaddr);
  96     }
  97     panic_if(!handled, "Page table fault when accessing virtual address %#x",
  98              vaddr);
  99
 100 }
 101
 102 void
 103 GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 104 {
 105     panic("Alignment fault when accessing virtual address %#x\n", vaddr);
 106 }
 107
 108 void GenericHtmFailureFault::invoke(ThreadContext *tc,
 109                                     const StaticInstPtr &inst)
 110 {
 111     // reset decoder
 112     TheISA::Decoder* dcdr = tc->getDecoderPtr();
 113     dcdr->reset();
 114
 115     // restore transaction checkpoint
 116     const auto& checkpoint = tc->getHtmCheckpointPtr();
 117     assert(checkpoint);
 118     assert(checkpoint->valid());
 119
 120     checkpoint->restore(tc, getHtmFailureFaultCause());
 121
 122     // reset the global monitor
 123     TheISA::globalClearExclusive(tc);
 124
 125     // send abort packet to ruby (in final breath)
 126     tc->htmAbortTransaction(htmUid, cause);
 127 }