2 * Copyright (c) 2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
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14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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40 * Authors: Steve Reinhardt
44 #ifndef __INSTRECORD_HH__
45 #define __INSTRECORD_HH__
47 #include "base/types.hh"
48 #include "cpu/inst_seq.hh"
49 #include "cpu/static_inst.hh"
50 #include "sim/sim_object.hh"
61 // The following fields are initialized by the constructor and
62 // thus guaranteed to be valid.
63 ThreadContext *thread;
64 // need to make this ref-counted so it doesn't go away before we
66 StaticInstPtr staticInst;
68 StaticInstPtr macroStaticInst;
70 // The remaining fields are only valid for particular instruction
71 // types (e.g, addresses for memory ops) or when particular
72 // options are enabled (e.g., tracing full register contents).
73 // Each data field has an associated valid flag to indicate
74 // whether the data field is valid.
78 * Memory request information in the instruction accessed memory.
81 Addr addr; ///< The address that was accessed
82 Addr size; ///< The size of the memory request
83 unsigned flags; ///< The flags that were assigned to the request.
88 * If this instruction wrote any data values they're recorded here
89 * WARNING: Instructions are quite loose with with what they write
90 * since many instructions write multiple values (e.g. destintation
91 * register, flags, status, ...) This only captures the last write.
92 * @TODO fix this and record all destintations that an instruction writes
100 /** @defgroup fetch_seq
101 * This records the serial number that the instruction was fetched in.
102 * @see fetch_seq_valid
104 InstSeqNum fetch_seq;
106 /** @defgroup commit_seq
107 * This records the instruction number that was committed in the pipeline
113 * What size of data was written?
117 DataInt8 = 1, // set to equal number of bytes
125 * Are the memory fields in the record valid?
129 /** @ingroup fetch_seq
130 * Are the fetch sequence number fields valid?
132 bool fetch_seq_valid;
133 /** @ingroup commit_seq
134 * Are the commit sequence number fields valid?
138 /** is the predicate for execution this inst true or false (not execed)?
143 InstRecord(Tick _when, ThreadContext *_thread,
144 const StaticInstPtr _staticInst,
146 const StaticInstPtr _macroStaticInst = NULL)
147 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
148 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
149 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
150 fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
153 virtual ~InstRecord() { }
155 void setWhen(Tick new_when) { when = new_when; }
156 void setMem(Addr a, Addr s, unsigned f)
158 addr = a; size = s; flags = f; mem_valid = true;
161 template <typename T, size_t N>
163 setData(std::array<T, N> d)
166 data_status = (DataStatus)sizeof(T);
167 static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
168 sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
169 "Type T has an unrecognized size.");
172 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
173 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
174 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
175 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
177 void setData(int64_t d) { setData((uint64_t)d); }
178 void setData(int32_t d) { setData((uint32_t)d); }
179 void setData(int16_t d) { setData((uint16_t)d); }
180 void setData(int8_t d) { setData((uint8_t)d); }
182 void setData(double d) { data.as_double = d; data_status = DataDouble; }
184 void setFetchSeq(InstSeqNum seq)
185 { fetch_seq = seq; fetch_seq_valid = true; }
187 void setCPSeq(InstSeqNum seq)
188 { cp_seq = seq; cp_seq_valid = true; }
190 void setPredicate(bool val) { predicate = val; }
192 virtual void dump() = 0;
195 Tick getWhen() const { return when; }
196 ThreadContext *getThread() const { return thread; }
197 StaticInstPtr getStaticInst() const { return staticInst; }
198 TheISA::PCState getPCState() const { return pc; }
199 StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
201 Addr getAddr() const { return addr; }
202 Addr getSize() const { return size; }
203 unsigned getFlags() const { return flags; }
204 bool getMemValid() const { return mem_valid; }
206 uint64_t getIntData() const { return data.as_int; }
207 double getFloatData() const { return data.as_double; }
208 int getDataStatus() const { return data_status; }
210 InstSeqNum getFetchSeq() const { return fetch_seq; }
211 bool getFetchSeqValid() const { return fetch_seq_valid; }
213 InstSeqNum getCpSeq() const { return cp_seq; }
214 bool getCpSeqValid() const { return cp_seq_valid; }
217 class InstTracer : public SimObject
220 InstTracer(const Params *p) : SimObject(p)
223 virtual ~InstTracer()
227 getInstRecord(Tick when, ThreadContext *tc,
228 const StaticInstPtr staticInst, TheISA::PCState pc,
229 const StaticInstPtr macroStaticInst = NULL) = 0;
236 #endif // __INSTRECORD_HH__