src/sim/probe/mem.hh

   1 /*
   2  * Copyright (c) 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __SIM_PROBE_MEM_HH__
  39 #define __SIM_PROBE_MEM_HH__
  40
  41 #include <memory>
  42
  43 #include "mem/packet.hh"
  44 #include "sim/probe/probe.hh"
  45
  46 namespace ProbePoints {
  47
  48 /**
  49  * A struct to hold on to the essential fields from a packet, so that
  50  * the packet and underlying request can be safely passed on, and
  51  * consequently modified or even deleted.
  52  */
  53 struct PacketInfo {
  54     MemCmd cmd;
  55     Addr addr;
  56     uint32_t size;
  57     Request::FlagsType flags;
  58     Addr pc;
  59     RequestorID id;
  60
  61     explicit PacketInfo(const PacketPtr& pkt) :
  62         cmd(pkt->cmd),
  63         addr(pkt->getAddr()),
  64         size(pkt->getSize()),
  65         flags(pkt->req->getFlags()),
  66         pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
  67         id(pkt->req->requestorId())  { }
  68 };
  69
  70 /**
  71  * Packet probe point
  72  *
  73  * This probe point provides a unified interface for components that
  74  * want to instrument Packets in the memory system. Components should
  75  * when possible adhere to the following naming scheme:
  76  *
  77  * <ul>
  78  *
  79  *   <li>PktRequest: Requests sent out on the memory side of a normal
  80  *       components and incoming requests for memories. Packets should
  81  *       not be duplicated (i.e., a packet should only appear once
  82  *       irrespective of the receiving end requesting a retry).
  83  *
  84  *   <li>PktResponse: Response received from the memory side of a
  85  *       normal component or a response being sent out from a memory.
  86  *
  87  *   <li>PktRequestCPU: Incoming, accepted, memory request on the CPU
  88  *       side of a two-sided component. This probe point is primarily
  89  *       intended for components that cache or forward requests (e.g.,
  90  *       caches and XBars), single-sided components should use
  91  *       PktRequest instead. The probe point should only be called
  92  *       when a packet is accepted.
  93  *
  94  *   <li>PktResponseCPU: Outgoing response memory request on the CPU
  95  *       side of a two-sided component. This probe point is primarily
  96  *       intended for components that cache or forward requests (e.g.,
  97  *       caches and XBars), single-sided components should use
  98  *       PktRequest instead.
  99  *
 100  * </ul>
 101  *
 102  */
 103 typedef ProbePointArg<PacketInfo> Packet;
 104 typedef std::unique_ptr<Packet> PacketUPtr;
 105
 106 }
 107
 108 #endif