3c2a27f5454034ea6171ff26f7e1fe225a536c2a
[gem5.git] / src / sim / pseudo_inst.cc
1 /*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31 #include <errno.h>
32 #include <fcntl.h>
33 #include <unistd.h>
34
35 #include <fstream>
36 #include <string>
37
38 #include "arch/kernel_stats.hh"
39 #include "arch/vtophys.hh"
40 #include "base/debug.hh"
41 #include "cpu/base.hh"
42 #include "cpu/thread_context.hh"
43 #include "cpu/quiesce_event.hh"
44 #include "params/BaseCPU.hh"
45 #include "sim/pseudo_inst.hh"
46 #include "sim/serialize.hh"
47 #include "sim/sim_events.hh"
48 #include "sim/sim_exit.hh"
49 #include "sim/stat_control.hh"
50 #include "sim/stats.hh"
51 #include "sim/system.hh"
52 #if FULL_SYSTEM
53 #include "sim/vptr.hh"
54 #endif
55
56 using namespace std;
57
58 using namespace Stats;
59 using namespace TheISA;
60
61 namespace PseudoInst {
62
63 #if FULL_SYSTEM
64
65 void
66 arm(ThreadContext *tc)
67 {
68 if (tc->getKernelStats())
69 tc->getKernelStats()->arm();
70 }
71
72 void
73 quiesce(ThreadContext *tc)
74 {
75 if (!tc->getCpuPtr()->params()->do_quiesce)
76 return;
77
78 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
79
80 tc->suspend();
81 if (tc->getKernelStats())
82 tc->getKernelStats()->quiesce();
83 }
84
85 void
86 quiesceNs(ThreadContext *tc, uint64_t ns)
87 {
88 if (!tc->getCpuPtr()->params()->do_quiesce || ns == 0)
89 return;
90
91 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
92
93 Tick resume = curTick + Clock::Int::ns * ns;
94
95 mainEventQueue.reschedule(quiesceEvent, resume, true);
96
97 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
98 tc->getCpuPtr()->name(), ns, resume);
99
100 tc->suspend();
101 if (tc->getKernelStats())
102 tc->getKernelStats()->quiesce();
103 }
104
105 void
106 quiesceCycles(ThreadContext *tc, uint64_t cycles)
107 {
108 if (!tc->getCpuPtr()->params()->do_quiesce || cycles == 0)
109 return;
110
111 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
112
113 Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
114
115 mainEventQueue.reschedule(quiesceEvent, resume, true);
116
117 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
118 tc->getCpuPtr()->name(), cycles, resume);
119
120 tc->suspend();
121 if (tc->getKernelStats())
122 tc->getKernelStats()->quiesce();
123 }
124
125 uint64_t
126 quiesceTime(ThreadContext *tc)
127 {
128 return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
129 }
130
131 #endif
132
133 uint64_t
134 rpns(ThreadContext *tc)
135 {
136 return curTick / Clock::Int::ns;
137 }
138
139 void
140 wakeCPU(ThreadContext *tc, uint64_t cpuid)
141 {
142 System *sys = tc->getSystemPtr();
143 ThreadContext *other_tc = sys->threadContexts[cpuid];
144 if (other_tc->status() == ThreadContext::Suspended)
145 other_tc->activate();
146 }
147
148 void
149 m5exit(ThreadContext *tc, Tick delay)
150 {
151 Tick when = curTick + delay * Clock::Int::ns;
152 Event *event = new SimLoopExitEvent("m5_exit instruction encountered", 0);
153 mainEventQueue.schedule(event, when);
154 }
155
156 #if FULL_SYSTEM
157
158 void
159 loadsymbol(ThreadContext *tc)
160 {
161 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
162 if (filename.empty()) {
163 return;
164 }
165
166 std::string buffer;
167 ifstream file(filename.c_str());
168
169 if (!file)
170 fatal("file error: Can't open symbol table file %s\n", filename);
171
172 while (!file.eof()) {
173 getline(file, buffer);
174
175 if (buffer.empty())
176 continue;
177
178 int idx = buffer.find(' ');
179 if (idx == string::npos)
180 continue;
181
182 string address = "0x" + buffer.substr(0, idx);
183 eat_white(address);
184 if (address.empty())
185 continue;
186
187 // Skip over letter and space
188 string symbol = buffer.substr(idx + 3);
189 eat_white(symbol);
190 if (symbol.empty())
191 continue;
192
193 Addr addr;
194 if (!to_number(address, addr))
195 continue;
196
197 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
198 continue;
199
200
201 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
202 }
203 file.close();
204 }
205
206 void
207 addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
208 {
209 char symb[100];
210 CopyStringOut(tc, symb, symbolAddr, 100);
211 std::string symbol(symb);
212
213 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
214
215 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
216 debugSymbolTable->insert(addr,symbol);
217 }
218
219 #endif
220
221
222 void
223 resetstats(ThreadContext *tc, Tick delay, Tick period)
224 {
225 if (!tc->getCpuPtr()->params()->do_statistics_insts)
226 return;
227
228
229 Tick when = curTick + delay * Clock::Int::ns;
230 Tick repeat = period * Clock::Int::ns;
231
232 Stats::StatEvent(false, true, when, repeat);
233 }
234
235 void
236 dumpstats(ThreadContext *tc, Tick delay, Tick period)
237 {
238 if (!tc->getCpuPtr()->params()->do_statistics_insts)
239 return;
240
241
242 Tick when = curTick + delay * Clock::Int::ns;
243 Tick repeat = period * Clock::Int::ns;
244
245 Stats::StatEvent(true, false, when, repeat);
246 }
247
248 void
249 dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
250 {
251 if (!tc->getCpuPtr()->params()->do_statistics_insts)
252 return;
253
254
255 Tick when = curTick + delay * Clock::Int::ns;
256 Tick repeat = period * Clock::Int::ns;
257
258 Stats::StatEvent(true, true, when, repeat);
259 }
260
261 void
262 m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
263 {
264 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
265 return;
266
267 Tick when = curTick + delay * Clock::Int::ns;
268 Tick repeat = period * Clock::Int::ns;
269
270 Event *event = new SimLoopExitEvent("checkpoint", 0, repeat);
271 mainEventQueue.schedule(event, when);
272 }
273
274 #if FULL_SYSTEM
275
276 uint64_t
277 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
278 {
279 const string &file = tc->getSystemPtr()->params()->readfile;
280 if (file.empty()) {
281 return ULL(0);
282 }
283
284 uint64_t result = 0;
285
286 int fd = ::open(file.c_str(), O_RDONLY, 0);
287 if (fd < 0)
288 panic("could not open file %s\n", file);
289
290 if (::lseek(fd, offset, SEEK_SET) < 0)
291 panic("could not seek: %s", strerror(errno));
292
293 char *buf = new char[len];
294 char *p = buf;
295 while (len > 0) {
296 int bytes = ::read(fd, p, len);
297 if (bytes <= 0)
298 break;
299
300 p += bytes;
301 result += bytes;
302 len -= bytes;
303 }
304
305 close(fd);
306 CopyIn(tc, vaddr, buf, result);
307 delete [] buf;
308 return result;
309 }
310
311 #endif
312
313 void
314 debugbreak(ThreadContext *tc)
315 {
316 debug_break();
317 }
318
319 void
320 switchcpu(ThreadContext *tc)
321 {
322 exitSimLoop("switchcpu");
323 }
324
325 /* namespace PseudoInst */ }