44fe2fcae8732a62781dff675808c20e5fb87bce
2 * Copyright (c) 2010-2012, 2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2011 Advanced Micro Devices, Inc.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Nathan Binkert
52 #include "arch/kernel_stats.hh"
53 #include "arch/utility.hh"
54 #include "arch/vtophys.hh"
55 #include "arch/pseudo_inst.hh"
56 #include "base/debug.hh"
57 #include "base/output.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/base.hh"
60 #include "cpu/quiesce_event.hh"
61 #include "cpu/thread_context.hh"
62 #include "debug/Loader.hh"
63 #include "debug/PseudoInst.hh"
64 #include "debug/Quiesce.hh"
65 #include "debug/WorkItems.hh"
66 #include "dev/net/dist_iface.hh"
67 #include "params/BaseCPU.hh"
68 #include "sim/full_system.hh"
69 #include "sim/initparam_keys.hh"
70 #include "sim/process.hh"
71 #include "sim/pseudo_inst.hh"
72 #include "sim/serialize.hh"
73 #include "sim/sim_events.hh"
74 #include "sim/sim_exit.hh"
75 #include "sim/stat_control.hh"
76 #include "sim/stats.hh"
77 #include "sim/system.hh"
78 #include "sim/vptr.hh"
82 using namespace Stats
;
83 using namespace TheISA
;
85 namespace PseudoInst
{
88 panicFsOnlyPseudoInst(const char *name
)
90 panic("Pseudo inst \"%s\" is only available in Full System mode.");
94 pseudoInst(ThreadContext
*tc
, uint8_t func
, uint8_t subfunc
)
98 DPRINTF(PseudoInst
, "PseudoInst::pseudoInst(%i, %i)\n", func
, subfunc
);
100 // We need to do this in a slightly convoluted way since
101 // getArgument() might have side-effects on arg_num. We could have
102 // used the Argument class, but due to the possible side effects
103 // from getArgument, it'd most likely break.
105 for (int i
= 0; i
< sizeof(args
) / sizeof(*args
); ++i
) {
106 args
[arg_num
] = getArgument(tc
, arg_num
, sizeof(uint64_t), false);
111 case 0x00: // arm_func
115 case 0x01: // quiesce_func
119 case 0x02: // quiescens_func
123 case 0x03: // quiescecycle_func
124 quiesceNs(tc
, args
[0]);
127 case 0x04: // quiescetime_func
128 return quiesceTime(tc
);
130 case 0x07: // rpns_func
133 case 0x09: // wakecpu_func
134 wakeCPU(tc
, args
[0]);
137 case 0x21: // exit_func
142 m5fail(tc
, args
[0], args
[1]);
145 case 0x30: // initparam_func
146 return initParam(tc
, args
[0], args
[1]);
148 case 0x31: // loadsymbol_func
152 case 0x40: // resetstats_func
153 resetstats(tc
, args
[0], args
[1]);
156 case 0x41: // dumpstats_func
157 dumpstats(tc
, args
[0], args
[1]);
160 case 0x42: // dumprststats_func
161 dumpresetstats(tc
, args
[0], args
[1]);
164 case 0x43: // ckpt_func
165 m5checkpoint(tc
, args
[0], args
[1]);
168 case 0x4f: // writefile_func
169 return writefile(tc
, args
[0], args
[1], args
[2], args
[3]);
171 case 0x50: // readfile_func
172 return readfile(tc
, args
[0], args
[1], args
[2]);
174 case 0x51: // debugbreak_func
178 case 0x52: // switchcpu_func
182 case 0x53: // addsymbol_func
183 addsymbol(tc
, args
[0], args
[1]);
186 case 0x54: // panic_func
187 panic("M5 panic instruction called at %s\n", tc
->pcState());
189 case 0x5a: // work_begin_func
190 workbegin(tc
, args
[0], args
[1]);
193 case 0x5b: // work_end_func
194 workend(tc
, args
[0], args
[1]);
197 case 0x55: // annotate_func
198 case 0x56: // reserved2_func
199 case 0x57: // reserved3_func
200 case 0x58: // reserved4_func
201 case 0x59: // reserved5_func
202 warn("Unimplemented m5 op (0x%x)\n", func
);
205 /* SE mode functions */
206 case 0x60: // syscall_func
210 case 0x61: // pagefault_func
215 warn("Unhandled m5 op: 0x%x\n", func
);
223 arm(ThreadContext
*tc
)
225 DPRINTF(PseudoInst
, "PseudoInst::arm()\n");
227 panicFsOnlyPseudoInst("arm");
229 if (tc
->getKernelStats())
230 tc
->getKernelStats()->arm();
234 quiesce(ThreadContext
*tc
)
236 DPRINTF(PseudoInst
, "PseudoInst::quiesce()\n");
238 panicFsOnlyPseudoInst("quiesce");
240 if (!tc
->getCpuPtr()->params()->do_quiesce
)
243 DPRINTF(Quiesce
, "%s: quiesce()\n", tc
->getCpuPtr()->name());
246 if (tc
->getKernelStats())
247 tc
->getKernelStats()->quiesce();
251 quiesceSkip(ThreadContext
*tc
)
253 DPRINTF(PseudoInst
, "PseudoInst::quiesceSkip()\n");
255 panicFsOnlyPseudoInst("quiesceSkip");
257 BaseCPU
*cpu
= tc
->getCpuPtr();
259 if (!cpu
->params()->do_quiesce
)
262 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
264 Tick resume
= curTick() + 1;
266 cpu
->reschedule(quiesceEvent
, resume
, true);
268 DPRINTF(Quiesce
, "%s: quiesceSkip() until %d\n",
269 cpu
->name(), resume
);
272 if (tc
->getKernelStats())
273 tc
->getKernelStats()->quiesce();
277 quiesceNs(ThreadContext
*tc
, uint64_t ns
)
279 DPRINTF(PseudoInst
, "PseudoInst::quiesceNs(%i)\n", ns
);
281 panicFsOnlyPseudoInst("quiesceNs");
283 BaseCPU
*cpu
= tc
->getCpuPtr();
285 if (!cpu
->params()->do_quiesce
)
288 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
290 Tick resume
= curTick() + SimClock::Int::ns
* ns
;
292 cpu
->reschedule(quiesceEvent
, resume
, true);
294 DPRINTF(Quiesce
, "%s: quiesceNs(%d) until %d\n",
295 cpu
->name(), ns
, resume
);
298 if (tc
->getKernelStats())
299 tc
->getKernelStats()->quiesce();
303 quiesceCycles(ThreadContext
*tc
, uint64_t cycles
)
305 DPRINTF(PseudoInst
, "PseudoInst::quiesceCycles(%i)\n", cycles
);
307 panicFsOnlyPseudoInst("quiesceCycles");
309 BaseCPU
*cpu
= tc
->getCpuPtr();
311 if (!cpu
->params()->do_quiesce
)
314 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
316 Tick resume
= cpu
->clockEdge(Cycles(cycles
));
318 cpu
->reschedule(quiesceEvent
, resume
, true);
320 DPRINTF(Quiesce
, "%s: quiesceCycles(%d) until %d\n",
321 cpu
->name(), cycles
, resume
);
324 if (tc
->getKernelStats())
325 tc
->getKernelStats()->quiesce();
329 quiesceTime(ThreadContext
*tc
)
331 DPRINTF(PseudoInst
, "PseudoInst::quiesceTime()\n");
333 panicFsOnlyPseudoInst("quiesceTime");
337 return (tc
->readLastActivate() - tc
->readLastSuspend()) /
342 rpns(ThreadContext
*tc
)
344 DPRINTF(PseudoInst
, "PseudoInst::rpns()\n");
345 return curTick() / SimClock::Int::ns
;
349 wakeCPU(ThreadContext
*tc
, uint64_t cpuid
)
351 DPRINTF(PseudoInst
, "PseudoInst::wakeCPU(%i)\n", cpuid
);
352 System
*sys
= tc
->getSystemPtr();
353 ThreadContext
*other_tc
= sys
->threadContexts
[cpuid
];
354 if (other_tc
->status() == ThreadContext::Suspended
)
355 other_tc
->activate();
359 m5exit(ThreadContext
*tc
, Tick delay
)
361 DPRINTF(PseudoInst
, "PseudoInst::m5exit(%i)\n", delay
);
362 if (DistIface::readyToExit(delay
)) {
363 Tick when
= curTick() + delay
* SimClock::Int::ns
;
364 exitSimLoop("m5_exit instruction encountered", 0, when
, 0, true);
369 m5fail(ThreadContext
*tc
, Tick delay
, uint64_t code
)
371 DPRINTF(PseudoInst
, "PseudoInst::m5fail(%i, %i)\n", delay
, code
);
372 Tick when
= curTick() + delay
* SimClock::Int::ns
;
373 exitSimLoop("m5_fail instruction encountered", code
, when
, 0, true);
377 loadsymbol(ThreadContext
*tc
)
379 DPRINTF(PseudoInst
, "PseudoInst::loadsymbol()\n");
381 panicFsOnlyPseudoInst("loadsymbol");
383 const string
&filename
= tc
->getCpuPtr()->system
->params()->symbolfile
;
384 if (filename
.empty()) {
389 ifstream
file(filename
.c_str());
392 fatal("file error: Can't open symbol table file %s\n", filename
);
394 while (!file
.eof()) {
395 getline(file
, buffer
);
400 string::size_type idx
= buffer
.find(' ');
401 if (idx
== string::npos
)
404 string address
= "0x" + buffer
.substr(0, idx
);
409 // Skip over letter and space
410 string symbol
= buffer
.substr(idx
+ 3);
416 if (!to_number(address
, addr
))
419 if (!tc
->getSystemPtr()->kernelSymtab
->insert(addr
, symbol
))
423 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
429 addsymbol(ThreadContext
*tc
, Addr addr
, Addr symbolAddr
)
431 DPRINTF(PseudoInst
, "PseudoInst::addsymbol(0x%x, 0x%x)\n",
434 panicFsOnlyPseudoInst("addSymbol");
437 CopyStringOut(tc
, symb
, symbolAddr
, 100);
438 std::string
symbol(symb
);
440 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
442 tc
->getSystemPtr()->kernelSymtab
->insert(addr
,symbol
);
443 debugSymbolTable
->insert(addr
,symbol
);
447 initParam(ThreadContext
*tc
, uint64_t key_str1
, uint64_t key_str2
)
449 DPRINTF(PseudoInst
, "PseudoInst::initParam() key:%s%s\n", (char *)&key_str1
,
452 panicFsOnlyPseudoInst("initParam");
456 // The key parameter string is passed in via two 64-bit registers. We copy
457 // out the characters from the 64-bit integer variables here and concatenate
458 // them in the key_str character buffer
459 const int len
= 2 * sizeof(uint64_t) + 1;
461 memset(key_str
, '\0', len
);
463 assert(key_str2
== 0);
465 strncpy(key_str
, (char *)&key_str1
, sizeof(uint64_t));
468 if (strlen(key_str
) == sizeof(uint64_t)) {
469 strncpy(key_str
+ sizeof(uint64_t), (char *)&key_str2
,
472 assert(key_str2
== 0);
475 // Compare the key parameter with the known values to select the return
478 if (strcmp(key_str
, InitParamKey::DEFAULT
) == 0) {
479 val
= tc
->getCpuPtr()->system
->init_param
;
480 } else if (strcmp(key_str
, InitParamKey::DIST_RANK
) == 0) {
481 val
= DistIface::rankParam();
482 } else if (strcmp(key_str
, InitParamKey::DIST_SIZE
) == 0) {
483 val
= DistIface::sizeParam();
485 panic("Unknown key for initparam pseudo instruction:\"%s\"", key_str
);
492 resetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
494 DPRINTF(PseudoInst
, "PseudoInst::resetstats(%i, %i)\n", delay
, period
);
495 if (!tc
->getCpuPtr()->params()->do_statistics_insts
)
499 Tick when
= curTick() + delay
* SimClock::Int::ns
;
500 Tick repeat
= period
* SimClock::Int::ns
;
502 Stats::schedStatEvent(false, true, when
, repeat
);
506 dumpstats(ThreadContext
*tc
, Tick delay
, Tick period
)
508 DPRINTF(PseudoInst
, "PseudoInst::dumpstats(%i, %i)\n", delay
, period
);
509 if (!tc
->getCpuPtr()->params()->do_statistics_insts
)
513 Tick when
= curTick() + delay
* SimClock::Int::ns
;
514 Tick repeat
= period
* SimClock::Int::ns
;
516 Stats::schedStatEvent(true, false, when
, repeat
);
520 dumpresetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
522 DPRINTF(PseudoInst
, "PseudoInst::dumpresetstats(%i, %i)\n", delay
, period
);
523 if (!tc
->getCpuPtr()->params()->do_statistics_insts
)
527 Tick when
= curTick() + delay
* SimClock::Int::ns
;
528 Tick repeat
= period
* SimClock::Int::ns
;
530 Stats::schedStatEvent(true, true, when
, repeat
);
534 m5checkpoint(ThreadContext
*tc
, Tick delay
, Tick period
)
536 DPRINTF(PseudoInst
, "PseudoInst::m5checkpoint(%i, %i)\n", delay
, period
);
537 if (!tc
->getCpuPtr()->params()->do_checkpoint_insts
)
540 if (DistIface::readyToCkpt(delay
, period
)) {
541 Tick when
= curTick() + delay
* SimClock::Int::ns
;
542 Tick repeat
= period
* SimClock::Int::ns
;
543 exitSimLoop("checkpoint", 0, when
, repeat
);
548 readfile(ThreadContext
*tc
, Addr vaddr
, uint64_t len
, uint64_t offset
)
550 DPRINTF(PseudoInst
, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
553 panicFsOnlyPseudoInst("readfile");
557 const string
&file
= tc
->getSystemPtr()->params()->readfile
;
564 int fd
= ::open(file
.c_str(), O_RDONLY
, 0);
566 panic("could not open file %s\n", file
);
568 if (::lseek(fd
, offset
, SEEK_SET
) < 0)
569 panic("could not seek: %s", strerror(errno
));
571 char *buf
= new char[len
];
574 int bytes
= ::read(fd
, p
, len
);
584 CopyIn(tc
, vaddr
, buf
, result
);
590 writefile(ThreadContext
*tc
, Addr vaddr
, uint64_t len
, uint64_t offset
,
593 DPRINTF(PseudoInst
, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n",
594 vaddr
, len
, offset
, filename_addr
);
596 // copy out target filename
598 std::string filename
;
599 CopyStringOut(tc
, fn
, filename_addr
, 100);
600 filename
= std::string(fn
);
604 // create a new file (truncate)
605 out
= simout
.create(filename
, true, true);
607 // do not truncate file if offset is non-zero
608 // (ios::in flag is required as well to keep the existing data
609 // intact, otherwise existing data will be zeroed out.)
610 out
= simout
.open(filename
, ios::in
| ios::out
| ios::binary
, true);
613 ostream
*os(out
->stream());
615 panic("could not open file %s\n", filename
);
620 // copy out data and write to file
621 char *buf
= new char[len
];
622 CopyOut(tc
, buf
, vaddr
, len
);
624 if (os
->fail() || os
->bad())
625 panic("Error while doing writefile!\n");
635 debugbreak(ThreadContext
*tc
)
637 DPRINTF(PseudoInst
, "PseudoInst::debugbreak()\n");
642 switchcpu(ThreadContext
*tc
)
644 DPRINTF(PseudoInst
, "PseudoInst::switchcpu()\n");
645 exitSimLoop("switchcpu");
649 // This function is executed when annotated work items begin. Depending on
650 // what the user specified at the command line, the simulation may exit and/or
651 // take a checkpoint when a certain work item begins.
654 workbegin(ThreadContext
*tc
, uint64_t workid
, uint64_t threadid
)
656 DPRINTF(PseudoInst
, "PseudoInst::workbegin(%i, %i)\n", workid
, threadid
);
657 System
*sys
= tc
->getSystemPtr();
658 const System::Params
*params
= sys
->params();
660 if (params
->exit_on_work_items
) {
661 exitSimLoop("workbegin", static_cast<int>(workid
));
665 DPRINTF(WorkItems
, "Work Begin workid: %d, threadid %d\n", workid
,
667 tc
->getCpuPtr()->workItemBegin();
668 sys
->workItemBegin(threadid
, workid
);
671 // If specified, determine if this is the specific work item the user
674 if (params
->work_item_id
== -1 || params
->work_item_id
== workid
) {
676 uint64_t systemWorkBeginCount
= sys
->incWorkItemsBegin();
677 int cpuId
= tc
->getCpuPtr()->cpuId();
679 if (params
->work_cpus_ckpt_count
!= 0 &&
680 sys
->markWorkItem(cpuId
) >= params
->work_cpus_ckpt_count
) {
682 // If active cpus equals checkpoint count, create checkpoint
684 exitSimLoop("checkpoint");
687 if (systemWorkBeginCount
== params
->work_begin_ckpt_count
) {
689 // Note: the string specified as the cause of the exit event must
690 // exactly equal "checkpoint" inorder to create a checkpoint
692 exitSimLoop("checkpoint");
695 if (systemWorkBeginCount
== params
->work_begin_exit_count
) {
697 // If a certain number of work items started, exit simulation
699 exitSimLoop("work started count reach");
702 if (cpuId
== params
->work_begin_cpu_id_exit
) {
704 // If work started on the cpu id specified, exit simulation
706 exitSimLoop("work started on specific cpu");
712 // This function is executed when annotated work items end. Depending on
713 // what the user specified at the command line, the simulation may exit and/or
714 // take a checkpoint when a certain work item ends.
717 workend(ThreadContext
*tc
, uint64_t workid
, uint64_t threadid
)
719 DPRINTF(PseudoInst
, "PseudoInst::workend(%i, %i)\n", workid
, threadid
);
720 System
*sys
= tc
->getSystemPtr();
721 const System::Params
*params
= sys
->params();
723 if (params
->exit_on_work_items
) {
724 exitSimLoop("workend", static_cast<int>(workid
));
728 DPRINTF(WorkItems
, "Work End workid: %d, threadid %d\n", workid
, threadid
);
729 tc
->getCpuPtr()->workItemEnd();
730 sys
->workItemEnd(threadid
, workid
);
733 // If specified, determine if this is the specific work item the user
736 if (params
->work_item_id
== -1 || params
->work_item_id
== workid
) {
738 uint64_t systemWorkEndCount
= sys
->incWorkItemsEnd();
739 int cpuId
= tc
->getCpuPtr()->cpuId();
741 if (params
->work_cpus_ckpt_count
!= 0 &&
742 sys
->markWorkItem(cpuId
) >= params
->work_cpus_ckpt_count
) {
744 // If active cpus equals checkpoint count, create checkpoint
746 exitSimLoop("checkpoint");
749 if (params
->work_end_ckpt_count
!= 0 &&
750 systemWorkEndCount
== params
->work_end_ckpt_count
) {
752 // If total work items completed equals checkpoint count, create
755 exitSimLoop("checkpoint");
758 if (params
->work_end_exit_count
!= 0 &&
759 systemWorkEndCount
== params
->work_end_exit_count
) {
761 // If total work items completed equals exit count, exit simulation
763 exitSimLoop("work items exit count reached");
768 } // namespace PseudoInst