Merge zizzer:/bk/newmem
[gem5.git] / src / sim / pseudo_inst.cc
1 /*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31 #include <errno.h>
32 #include <fcntl.h>
33 #include <unistd.h>
34
35 #include <string>
36
37 #include "sim/pseudo_inst.hh"
38 #include "arch/vtophys.hh"
39 #include "cpu/base.hh"
40 #include "cpu/thread_context.hh"
41 #include "cpu/quiesce_event.hh"
42 #include "kern/kernel_stats.hh"
43 #include "sim/param.hh"
44 #include "sim/serialize.hh"
45 #include "sim/sim_exit.hh"
46 #include "sim/stat_control.hh"
47 #include "sim/stats.hh"
48 #include "sim/system.hh"
49 #include "sim/debug.hh"
50 #include "sim/vptr.hh"
51
52 using namespace std;
53
54 using namespace Stats;
55 using namespace TheISA;
56
57 namespace AlphaPseudo
58 {
59 bool doStatisticsInsts;
60 bool doCheckpointInsts;
61 bool doQuiesce;
62
63 void
64 arm(ThreadContext *tc)
65 {
66 if (tc->getKernelStats())
67 tc->getKernelStats()->arm();
68 }
69
70 void
71 quiesce(ThreadContext *tc)
72 {
73 if (!doQuiesce)
74 return;
75
76 tc->suspend();
77 if (tc->getKernelStats())
78 tc->getKernelStats()->quiesce();
79 }
80
81 void
82 quiesceNs(ThreadContext *tc, uint64_t ns)
83 {
84 if (!doQuiesce || ns == 0)
85 return;
86
87 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
88
89 if (quiesceEvent->scheduled())
90 quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
91 else
92 quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
93
94 tc->suspend();
95 if (tc->getKernelStats())
96 tc->getKernelStats()->quiesce();
97 }
98
99 void
100 quiesceCycles(ThreadContext *tc, uint64_t cycles)
101 {
102 if (!doQuiesce || cycles == 0)
103 return;
104
105 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
106
107 if (quiesceEvent->scheduled())
108 quiesceEvent->reschedule(curTick +
109 tc->getCpuPtr()->cycles(cycles));
110 else
111 quiesceEvent->schedule(curTick +
112 tc->getCpuPtr()->cycles(cycles));
113
114 tc->suspend();
115 if (tc->getKernelStats())
116 tc->getKernelStats()->quiesce();
117 }
118
119 uint64_t
120 quiesceTime(ThreadContext *tc)
121 {
122 return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
123 }
124
125 void
126 ivlb(ThreadContext *tc)
127 {
128 if (tc->getKernelStats())
129 tc->getKernelStats()->ivlb();
130 }
131
132 void
133 ivle(ThreadContext *tc)
134 {
135 }
136
137 void
138 m5exit_old(ThreadContext *tc)
139 {
140 exitSimLoop(curTick, "m5_exit_old instruction encountered");
141 }
142
143 void
144 m5exit(ThreadContext *tc, Tick delay)
145 {
146 Tick when = curTick + delay * Clock::Int::ns;
147 exitSimLoop(when, "m5_exit instruction encountered");
148 }
149
150 void
151 resetstats(ThreadContext *tc, Tick delay, Tick period)
152 {
153 if (!doStatisticsInsts)
154 return;
155
156
157 Tick when = curTick + delay * Clock::Int::ns;
158 Tick repeat = period * Clock::Int::ns;
159
160 using namespace Stats;
161 SetupEvent(Reset, when, repeat);
162 }
163
164 void
165 dumpstats(ThreadContext *tc, Tick delay, Tick period)
166 {
167 if (!doStatisticsInsts)
168 return;
169
170
171 Tick when = curTick + delay * Clock::Int::ns;
172 Tick repeat = period * Clock::Int::ns;
173
174 using namespace Stats;
175 SetupEvent(Dump, when, repeat);
176 }
177
178 void
179 addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
180 {
181 char symb[100];
182 CopyStringOut(tc, symb, symbolAddr, 100);
183 std::string symbol(symb);
184
185 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
186
187 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
188 }
189
190 void
191 dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
192 {
193 if (!doStatisticsInsts)
194 return;
195
196
197 Tick when = curTick + delay * Clock::Int::ns;
198 Tick repeat = period * Clock::Int::ns;
199
200 using namespace Stats;
201 SetupEvent(Dump|Reset, when, repeat);
202 }
203
204 void
205 m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
206 {
207 if (!doCheckpointInsts)
208 return;
209 exitSimLoop("checkpoint");
210 }
211
212 uint64_t
213 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
214 {
215 const string &file = tc->getCpuPtr()->system->params()->readfile;
216 if (file.empty()) {
217 return ULL(0);
218 }
219
220 uint64_t result = 0;
221
222 int fd = ::open(file.c_str(), O_RDONLY, 0);
223 if (fd < 0)
224 panic("could not open file %s\n", file);
225
226 if (::lseek(fd, offset, SEEK_SET) < 0)
227 panic("could not seek: %s", strerror(errno));
228
229 char *buf = new char[len];
230 char *p = buf;
231 while (len > 0) {
232 int bytes = ::read(fd, p, len);
233 if (bytes <= 0)
234 break;
235
236 p += bytes;
237 result += bytes;
238 len -= bytes;
239 }
240
241 close(fd);
242 CopyIn(tc, vaddr, buf, result);
243 delete [] buf;
244 return result;
245 }
246
247 class Context : public ParamContext
248 {
249 public:
250 Context(const string &section) : ParamContext(section) {}
251 void checkParams();
252 };
253
254 Context context("pseudo_inst");
255
256 Param<bool> __quiesce(&context, "quiesce",
257 "enable quiesce instructions",
258 true);
259 Param<bool> __statistics(&context, "statistics",
260 "enable statistics pseudo instructions",
261 true);
262 Param<bool> __checkpoint(&context, "checkpoint",
263 "enable checkpoint pseudo instructions",
264 true);
265
266 void
267 Context::checkParams()
268 {
269 doQuiesce = __quiesce;
270 doStatisticsInsts = __statistics;
271 doCheckpointInsts = __checkpoint;
272 }
273
274 void debugbreak(ThreadContext *tc)
275 {
276 debug_break();
277 }
278
279 void switchcpu(ThreadContext *tc)
280 {
281 exitSimLoop("switchcpu");
282 }
283 }