2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
37 #include "sim/pseudo_inst.hh"
38 #include "arch/vtophys.hh"
39 #include "cpu/base.hh"
40 #include "cpu/thread_context.hh"
41 #include "cpu/quiesce_event.hh"
42 #include "kern/kernel_stats.hh"
43 #include "sim/param.hh"
44 #include "sim/serialize.hh"
45 #include "sim/sim_exit.hh"
46 #include "sim/stat_control.hh"
47 #include "sim/stats.hh"
48 #include "sim/system.hh"
49 #include "sim/debug.hh"
50 #include "sim/vptr.hh"
54 using namespace Stats
;
55 using namespace TheISA
;
59 bool doStatisticsInsts
;
60 bool doCheckpointInsts
;
64 arm(ThreadContext
*tc
)
66 if (tc
->getKernelStats())
67 tc
->getKernelStats()->arm();
71 quiesce(ThreadContext
*tc
)
77 if (tc
->getKernelStats())
78 tc
->getKernelStats()->quiesce();
82 quiesceNs(ThreadContext
*tc
, uint64_t ns
)
84 if (!doQuiesce
|| ns
== 0)
87 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
89 if (quiesceEvent
->scheduled())
90 quiesceEvent
->reschedule(curTick
+ Clock::Int::ns
* ns
);
92 quiesceEvent
->schedule(curTick
+ Clock::Int::ns
* ns
);
95 if (tc
->getKernelStats())
96 tc
->getKernelStats()->quiesce();
100 quiesceCycles(ThreadContext
*tc
, uint64_t cycles
)
102 if (!doQuiesce
|| cycles
== 0)
105 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
107 if (quiesceEvent
->scheduled())
108 quiesceEvent
->reschedule(curTick
+
109 tc
->getCpuPtr()->cycles(cycles
));
111 quiesceEvent
->schedule(curTick
+
112 tc
->getCpuPtr()->cycles(cycles
));
115 if (tc
->getKernelStats())
116 tc
->getKernelStats()->quiesce();
120 quiesceTime(ThreadContext
*tc
)
122 return (tc
->readLastActivate() - tc
->readLastSuspend()) / Clock::Int::ns
;
126 ivlb(ThreadContext
*tc
)
128 if (tc
->getKernelStats())
129 tc
->getKernelStats()->ivlb();
133 ivle(ThreadContext
*tc
)
138 m5exit_old(ThreadContext
*tc
)
140 exitSimLoop(curTick
, "m5_exit_old instruction encountered");
144 m5exit(ThreadContext
*tc
, Tick delay
)
146 Tick when
= curTick
+ delay
* Clock::Int::ns
;
147 exitSimLoop(when
, "m5_exit instruction encountered");
151 resetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
153 if (!doStatisticsInsts
)
157 Tick when
= curTick
+ delay
* Clock::Int::ns
;
158 Tick repeat
= period
* Clock::Int::ns
;
160 using namespace Stats
;
161 SetupEvent(Reset
, when
, repeat
);
165 dumpstats(ThreadContext
*tc
, Tick delay
, Tick period
)
167 if (!doStatisticsInsts
)
171 Tick when
= curTick
+ delay
* Clock::Int::ns
;
172 Tick repeat
= period
* Clock::Int::ns
;
174 using namespace Stats
;
175 SetupEvent(Dump
, when
, repeat
);
179 addsymbol(ThreadContext
*tc
, Addr addr
, Addr symbolAddr
)
182 CopyStringOut(tc
, symb
, symbolAddr
, 100);
183 std::string
symbol(symb
);
185 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
187 tc
->getSystemPtr()->kernelSymtab
->insert(addr
,symbol
);
191 dumpresetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
193 if (!doStatisticsInsts
)
197 Tick when
= curTick
+ delay
* Clock::Int::ns
;
198 Tick repeat
= period
* Clock::Int::ns
;
200 using namespace Stats
;
201 SetupEvent(Dump
|Reset
, when
, repeat
);
205 m5checkpoint(ThreadContext
*tc
, Tick delay
, Tick period
)
207 if (!doCheckpointInsts
)
209 exitSimLoop("checkpoint");
213 readfile(ThreadContext
*tc
, Addr vaddr
, uint64_t len
, uint64_t offset
)
215 const string
&file
= tc
->getCpuPtr()->system
->params()->readfile
;
222 int fd
= ::open(file
.c_str(), O_RDONLY
, 0);
224 panic("could not open file %s\n", file
);
226 if (::lseek(fd
, offset
, SEEK_SET
) < 0)
227 panic("could not seek: %s", strerror(errno
));
229 char *buf
= new char[len
];
232 int bytes
= ::read(fd
, p
, len
);
242 CopyIn(tc
, vaddr
, buf
, result
);
247 class Context
: public ParamContext
250 Context(const string
§ion
) : ParamContext(section
) {}
254 Context
context("pseudo_inst");
256 Param
<bool> __quiesce(&context
, "quiesce",
257 "enable quiesce instructions",
259 Param
<bool> __statistics(&context
, "statistics",
260 "enable statistics pseudo instructions",
262 Param
<bool> __checkpoint(&context
, "checkpoint",
263 "enable checkpoint pseudo instructions",
267 Context::checkParams()
269 doQuiesce
= __quiesce
;
270 doStatisticsInsts
= __statistics
;
271 doCheckpointInsts
= __checkpoint
;
274 void debugbreak(ThreadContext
*tc
)
279 void switchcpu(ThreadContext
*tc
)
281 exitSimLoop("switchcpu");