2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
37 #include "arch/vtophys.hh"
38 #include "base/annotate.hh"
39 #include "cpu/base.hh"
40 #include "cpu/thread_context.hh"
41 #include "cpu/quiesce_event.hh"
42 #include "arch/kernel_stats.hh"
43 #include "sim/param.hh"
44 #include "sim/pseudo_inst.hh"
45 #include "sim/serialize.hh"
46 #include "sim/sim_exit.hh"
47 #include "sim/stat_control.hh"
48 #include "sim/stats.hh"
49 #include "sim/system.hh"
50 #include "sim/debug.hh"
51 #include "sim/vptr.hh"
55 using namespace Stats
;
56 using namespace TheISA
;
60 bool doStatisticsInsts
;
61 bool doCheckpointInsts
;
65 arm(ThreadContext
*tc
)
67 if (tc
->getKernelStats())
68 tc
->getKernelStats()->arm();
72 quiesce(ThreadContext
*tc
)
77 DPRINTF(Quiesce
, "%s: quiesce()\n", tc
->getCpuPtr()->name());
80 if (tc
->getKernelStats())
81 tc
->getKernelStats()->quiesce();
85 quiesceNs(ThreadContext
*tc
, uint64_t ns
)
87 if (!doQuiesce
|| ns
== 0)
90 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
92 Tick resume
= curTick
+ Clock::Int::ns
* ns
;
94 if (quiesceEvent
->scheduled())
95 quiesceEvent
->reschedule(resume
);
97 quiesceEvent
->schedule(resume
);
99 DPRINTF(Quiesce
, "%s: quiesceNs(%d) until %d\n",
100 tc
->getCpuPtr()->name(), ns
, resume
);
103 if (tc
->getKernelStats())
104 tc
->getKernelStats()->quiesce();
108 quiesceCycles(ThreadContext
*tc
, uint64_t cycles
)
110 if (!doQuiesce
|| cycles
== 0)
113 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
115 Tick resume
= curTick
+ tc
->getCpuPtr()->cycles(cycles
);
117 if (quiesceEvent
->scheduled())
118 quiesceEvent
->reschedule(resume
);
120 quiesceEvent
->schedule(resume
);
122 DPRINTF(Quiesce
, "%s: quiesceCycles(%d) until %d\n",
123 tc
->getCpuPtr()->name(), cycles
, resume
);
126 if (tc
->getKernelStats())
127 tc
->getKernelStats()->quiesce();
131 quiesceTime(ThreadContext
*tc
)
133 return (tc
->readLastActivate() - tc
->readLastSuspend()) / Clock::Int::ns
;
137 m5exit_old(ThreadContext
*tc
)
139 exitSimLoop("m5_exit_old instruction encountered");
143 m5exit(ThreadContext
*tc
, Tick delay
)
145 Tick when
= curTick
+ delay
* Clock::Int::ns
;
146 schedExitSimLoop("m5_exit instruction encountered", when
);
150 loadsymbol(ThreadContext
*tc
)
152 const string
&filename
= tc
->getCpuPtr()->system
->params()->symbolfile
;
153 if (filename
.empty()) {
158 ifstream
file(filename
.c_str());
161 fatal("file error: Can't open symbol table file %s\n", filename
);
163 while (!file
.eof()) {
164 getline(file
, buffer
);
169 int idx
= buffer
.find(' ');
170 if (idx
== string::npos
)
173 string address
= "0x" + buffer
.substr(0, idx
);
178 // Skip over letter and space
179 string symbol
= buffer
.substr(idx
+ 3);
185 if (!to_number(address
, addr
))
188 if (!tc
->getSystemPtr()->kernelSymtab
->insert(addr
, symbol
))
192 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
198 resetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
200 if (!doStatisticsInsts
)
204 Tick when
= curTick
+ delay
* Clock::Int::ns
;
205 Tick repeat
= period
* Clock::Int::ns
;
207 using namespace Stats
;
208 SetupEvent(Reset
, when
, repeat
);
212 dumpstats(ThreadContext
*tc
, Tick delay
, Tick period
)
214 if (!doStatisticsInsts
)
218 Tick when
= curTick
+ delay
* Clock::Int::ns
;
219 Tick repeat
= period
* Clock::Int::ns
;
221 using namespace Stats
;
222 SetupEvent(Dump
, when
, repeat
);
226 addsymbol(ThreadContext
*tc
, Addr addr
, Addr symbolAddr
)
229 CopyStringOut(tc
, symb
, symbolAddr
, 100);
230 std::string
symbol(symb
);
232 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
234 tc
->getSystemPtr()->kernelSymtab
->insert(addr
,symbol
);
238 anBegin(ThreadContext
*tc
, uint64_t cur
)
240 Annotate::annotations
.add(tc
->getSystemPtr(), 0, cur
>> 32, cur
&
245 anWait(ThreadContext
*tc
, uint64_t cur
, uint64_t wait
)
247 Annotate::annotations
.add(tc
->getSystemPtr(), 0, cur
>> 32, cur
&
248 0xFFFFFFFF, wait
>> 32, wait
& 0xFFFFFFFF);
253 dumpresetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
255 if (!doStatisticsInsts
)
259 Tick when
= curTick
+ delay
* Clock::Int::ns
;
260 Tick repeat
= period
* Clock::Int::ns
;
262 using namespace Stats
;
263 SetupEvent(Dump
|Reset
, when
, repeat
);
267 m5checkpoint(ThreadContext
*tc
, Tick delay
, Tick period
)
269 if (!doCheckpointInsts
)
272 Tick when
= curTick
+ delay
* Clock::Int::ns
;
273 Tick repeat
= period
* Clock::Int::ns
;
275 schedExitSimLoop("checkpoint", when
, repeat
);
279 readfile(ThreadContext
*tc
, Addr vaddr
, uint64_t len
, uint64_t offset
)
281 const string
&file
= tc
->getCpuPtr()->system
->params()->readfile
;
288 int fd
= ::open(file
.c_str(), O_RDONLY
, 0);
290 panic("could not open file %s\n", file
);
292 if (::lseek(fd
, offset
, SEEK_SET
) < 0)
293 panic("could not seek: %s", strerror(errno
));
295 char *buf
= new char[len
];
298 int bytes
= ::read(fd
, p
, len
);
308 CopyIn(tc
, vaddr
, buf
, result
);
313 class Context
: public ParamContext
316 Context(const string
§ion
) : ParamContext(section
) {}
320 Context
context("pseudo_inst");
322 Param
<bool> __quiesce(&context
, "quiesce",
323 "enable quiesce instructions",
325 Param
<bool> __statistics(&context
, "statistics",
326 "enable statistics pseudo instructions",
328 Param
<bool> __checkpoint(&context
, "checkpoint",
329 "enable checkpoint pseudo instructions",
333 Context::checkParams()
335 doQuiesce
= __quiesce
;
336 doStatisticsInsts
= __statistics
;
337 doCheckpointInsts
= __checkpoint
;
340 void debugbreak(ThreadContext
*tc
)
345 void switchcpu(ThreadContext
*tc
)
347 exitSimLoop("switchcpu");