2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
37 #include "sim/pseudo_inst.hh"
38 #include "arch/vtophys.hh"
39 #include "cpu/base.hh"
40 #include "cpu/sampler/sampler.hh"
41 #include "cpu/thread_context.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "kern/kernel_stats.hh"
44 #include "sim/param.hh"
45 #include "sim/serialize.hh"
46 #include "sim/sim_exit.hh"
47 #include "sim/stat_control.hh"
48 #include "sim/stats.hh"
49 #include "sim/system.hh"
50 #include "sim/debug.hh"
51 #include "sim/vptr.hh"
55 extern Sampler
*SampCPU
;
57 using namespace Stats
;
58 using namespace TheISA
;
62 bool doStatisticsInsts
;
63 bool doCheckpointInsts
;
67 arm(ThreadContext
*tc
)
69 if (tc
->getKernelStats())
70 tc
->getKernelStats()->arm();
74 quiesce(ThreadContext
*tc
)
80 if (tc
->getKernelStats())
81 tc
->getKernelStats()->quiesce();
85 quiesceNs(ThreadContext
*tc
, uint64_t ns
)
87 if (!doQuiesce
|| ns
== 0)
90 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
92 if (quiesceEvent
->scheduled())
93 quiesceEvent
->reschedule(curTick
+ Clock::Int::ns
* ns
);
95 quiesceEvent
->schedule(curTick
+ Clock::Int::ns
* ns
);
98 if (tc
->getKernelStats())
99 tc
->getKernelStats()->quiesce();
103 quiesceCycles(ThreadContext
*tc
, uint64_t cycles
)
105 if (!doQuiesce
|| cycles
== 0)
108 EndQuiesceEvent
*quiesceEvent
= tc
->getQuiesceEvent();
110 if (quiesceEvent
->scheduled())
111 quiesceEvent
->reschedule(curTick
+
112 tc
->getCpuPtr()->cycles(cycles
));
114 quiesceEvent
->schedule(curTick
+
115 tc
->getCpuPtr()->cycles(cycles
));
118 if (tc
->getKernelStats())
119 tc
->getKernelStats()->quiesce();
123 quiesceTime(ThreadContext
*tc
)
125 return (tc
->readLastActivate() - tc
->readLastSuspend()) / Clock::Int::ns
;
129 ivlb(ThreadContext
*tc
)
131 if (tc
->getKernelStats())
132 tc
->getKernelStats()->ivlb();
136 ivle(ThreadContext
*tc
)
141 m5exit_old(ThreadContext
*tc
)
143 exitSimLoop(curTick
, "m5_exit_old instruction encountered");
147 m5exit(ThreadContext
*tc
, Tick delay
)
149 Tick when
= curTick
+ delay
* Clock::Int::ns
;
150 exitSimLoop(when
, "m5_exit instruction encountered");
154 resetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
156 if (!doStatisticsInsts
)
160 Tick when
= curTick
+ delay
* Clock::Int::ns
;
161 Tick repeat
= period
* Clock::Int::ns
;
163 using namespace Stats
;
164 SetupEvent(Reset
, when
, repeat
);
168 dumpstats(ThreadContext
*tc
, Tick delay
, Tick period
)
170 if (!doStatisticsInsts
)
174 Tick when
= curTick
+ delay
* Clock::Int::ns
;
175 Tick repeat
= period
* Clock::Int::ns
;
177 using namespace Stats
;
178 SetupEvent(Dump
, when
, repeat
);
182 addsymbol(ThreadContext
*tc
, Addr addr
, Addr symbolAddr
)
185 CopyStringOut(tc
, symb
, symbolAddr
, 100);
186 std::string
symbol(symb
);
188 DPRINTF(Loader
, "Loaded symbol: %s @ %#llx\n", symbol
, addr
);
190 tc
->getSystemPtr()->kernelSymtab
->insert(addr
,symbol
);
194 dumpresetstats(ThreadContext
*tc
, Tick delay
, Tick period
)
196 if (!doStatisticsInsts
)
200 Tick when
= curTick
+ delay
* Clock::Int::ns
;
201 Tick repeat
= period
* Clock::Int::ns
;
203 using namespace Stats
;
204 SetupEvent(Dump
|Reset
, when
, repeat
);
208 m5checkpoint(ThreadContext
*tc
, Tick delay
, Tick period
)
210 if (!doCheckpointInsts
)
214 Tick when
= curTick
+ delay
* Clock::Int::ns
;
215 Tick repeat
= period
* Clock::Int::ns
;
217 Checkpoint::setup(when
, repeat
);
221 readfile(ThreadContext
*tc
, Addr vaddr
, uint64_t len
, uint64_t offset
)
223 const string
&file
= tc
->getCpuPtr()->system
->params()->readfile
;
230 int fd
= ::open(file
.c_str(), O_RDONLY
, 0);
232 panic("could not open file %s\n", file
);
234 if (::lseek(fd
, offset
, SEEK_SET
) < 0)
235 panic("could not seek: %s", strerror(errno
));
237 char *buf
= new char[len
];
240 int bytes
= ::read(fd
, p
, len
);
250 CopyIn(tc
, vaddr
, buf
, result
);
255 class Context
: public ParamContext
258 Context(const string
§ion
) : ParamContext(section
) {}
262 Context
context("pseudo_inst");
264 Param
<bool> __quiesce(&context
, "quiesce",
265 "enable quiesce instructions",
267 Param
<bool> __statistics(&context
, "statistics",
268 "enable statistics pseudo instructions",
270 Param
<bool> __checkpoint(&context
, "checkpoint",
271 "enable checkpoint pseudo instructions",
275 Context::checkParams()
277 doQuiesce
= __quiesce
;
278 doStatisticsInsts
= __statistics
;
279 doCheckpointInsts
= __checkpoint
;
282 void debugbreak(ThreadContext
*tc
)
287 void switchcpu(ThreadContext
*tc
)
290 SampCPU
->switchCPUs();