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41 #ifndef __SIM_PSEUDO_INST_HH__
42 #define __SIM_PSEUDO_INST_HH__
44 #include <gem5/asm/generic/m5ops.h>
48 #include "arch/pseudo_inst.hh"
49 #include "arch/utility.hh"
50 #include "base/types.hh" // For Tick and Addr data types.
51 #include "debug/PseudoInst.hh"
52 #include "sim/guest_abi.hh"
63 struct Result<PseudoInstABI, T>
66 store(ThreadContext *tc, const T &ret)
68 // Don't do anything with the pseudo inst results by default.
73 struct Argument<PseudoInstABI, uint64_t>
76 get(ThreadContext *tc, PseudoInstABI::State &state)
79 TheISA::getArgument(tc, state, sizeof(uint64_t), false);
85 } // namespace GuestABI
91 decodeAddrOffset(Addr offset, uint8_t &func)
93 func = bits(offset, 15, 8);
96 void arm(ThreadContext *tc);
97 void quiesce(ThreadContext *tc);
98 void quiesceSkip(ThreadContext *tc);
99 void quiesceNs(ThreadContext *tc, uint64_t ns);
100 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
101 uint64_t quiesceTime(ThreadContext *tc);
102 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
104 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
105 uint64_t offset, Addr filenameAddr);
106 void loadsymbol(ThreadContext *xc);
107 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
108 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
109 uint64_t rpns(ThreadContext *tc);
110 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
111 void m5exit(ThreadContext *tc, Tick delay);
112 void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
113 void resetstats(ThreadContext *tc, Tick delay, Tick period);
114 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
115 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
116 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
117 void debugbreak(ThreadContext *tc);
118 void switchcpu(ThreadContext *tc);
119 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
120 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
121 void m5Syscall(ThreadContext *tc);
122 void togglesync(ThreadContext *tc);
125 * Execute a decoded M5 pseudo instruction
127 * The ISA-specific code is responsible to decode the pseudo inst
128 * function number and subfunction number. After that has been done,
129 * the rest of the instruction can be implemented in an ISA-agnostic
130 * manner using the ISA-specific getArguments functions.
132 * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
133 * @param result A reference to a uint64_t to store a result in.
134 * @return Whether the pseudo instruction was recognized/handled.
137 template <typename ABI>
139 pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
141 DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
147 invokeSimcall<ABI>(tc, arm);
151 invokeSimcall<ABI>(tc, quiesce);
154 case M5OP_QUIESCE_NS:
155 invokeSimcall<ABI>(tc, quiesceNs);
158 case M5OP_QUIESCE_CYCLE:
159 invokeSimcall<ABI>(tc, quiesceCycles);
162 case M5OP_QUIESCE_TIME:
163 result = invokeSimcall<ABI>(tc, quiesceTime);
167 result = invokeSimcall<ABI>(tc, rpns);
171 invokeSimcall<ABI>(tc, wakeCPU);
175 invokeSimcall<ABI>(tc, m5exit);
179 invokeSimcall<ABI>(tc, m5fail);
182 case M5OP_INIT_PARAM:
183 result = invokeSimcall<ABI>(tc, initParam);
186 case M5OP_LOAD_SYMBOL:
187 invokeSimcall<ABI>(tc, loadsymbol);
190 case M5OP_RESET_STATS:
191 invokeSimcall<ABI>(tc, resetstats);
194 case M5OP_DUMP_STATS:
195 invokeSimcall<ABI>(tc, dumpstats);
198 case M5OP_DUMP_RESET_STATS:
199 invokeSimcall<ABI>(tc, dumpresetstats);
202 case M5OP_CHECKPOINT:
203 invokeSimcall<ABI>(tc, m5checkpoint);
206 case M5OP_WRITE_FILE:
207 result = invokeSimcall<ABI>(tc, writefile);
211 result = invokeSimcall<ABI>(tc, readfile);
214 case M5OP_DEBUG_BREAK:
215 invokeSimcall<ABI>(tc, debugbreak);
218 case M5OP_SWITCH_CPU:
219 invokeSimcall<ABI>(tc, switchcpu);
222 case M5OP_ADD_SYMBOL:
223 invokeSimcall<ABI>(tc, addsymbol);
227 panic("M5 panic instruction called at %s\n", tc->pcState());
229 case M5OP_WORK_BEGIN:
230 invokeSimcall<ABI>(tc, workbegin);
234 invokeSimcall<ABI>(tc, workend);
242 warn("Unimplemented m5 op (%#x)\n", func);
245 /* SE mode functions */
246 case M5OP_SE_SYSCALL:
247 invokeSimcall<ABI>(tc, m5Syscall);
250 case M5OP_SE_PAGE_FAULT:
251 invokeSimcall<ABI>(tc, TheISA::m5PageFault);
254 /* dist-gem5 functions */
255 case M5OP_DIST_TOGGLE_SYNC:
256 invokeSimcall<ABI>(tc, togglesync);
260 warn("Unhandled m5 op: %#x\n", func);
265 } // namespace PseudoInst
267 #endif // __SIM_PSEUDO_INST_HH__