src/sim/pseudo_inst.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __SIM_PSEUDO_INST_HH__
  42 #define __SIM_PSEUDO_INST_HH__
  43
  44 #include <gem5/asm/generic/m5ops.h>
  45
  46 class ThreadContext;
  47
  48 #include "arch/pseudo_inst.hh"
  49 #include "arch/utility.hh"
  50 #include "base/types.hh" // For Tick and Addr data types.
  51 #include "debug/PseudoInst.hh"
  52 #include "sim/guest_abi.hh"
  53
  54 struct PseudoInstABI
  55 {
  56     using State = int;
  57 };
  58
  59 namespace GuestABI
  60 {
  61
  62 template <typename T>
  63 struct Result<PseudoInstABI, T>
  64 {
  65     static void
  66     store(ThreadContext *tc, const T &ret)
  67     {
  68         // Don't do anything with the pseudo inst results by default.
  69     }
  70 };
  71
  72 template <>
  73 struct Argument<PseudoInstABI, uint64_t>
  74 {
  75     static uint64_t
  76     get(ThreadContext *tc, PseudoInstABI::State &state)
  77     {
  78         uint64_t result =
  79             TheISA::getArgument(tc, state, sizeof(uint64_t), false);
  80         state++;
  81         return result;
  82     }
  83 };
  84
  85 } // namespace GuestABI
  86
  87 namespace PseudoInst
  88 {
  89
  90 static inline void
  91 decodeAddrOffset(Addr offset, uint8_t &func)
  92 {
  93     func = bits(offset, 15, 8);
  94 }
  95
  96 void arm(ThreadContext *tc);
  97 void quiesce(ThreadContext *tc);
  98 void quiesceSkip(ThreadContext *tc);
  99 void quiesceNs(ThreadContext *tc, uint64_t ns);
 100 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
 101 uint64_t quiesceTime(ThreadContext *tc);
 102 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
 103     uint64_t offset);
 104 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
 105     uint64_t offset, Addr filenameAddr);
 106 void loadsymbol(ThreadContext *xc);
 107 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
 108 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
 109 uint64_t rpns(ThreadContext *tc);
 110 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
 111 void m5exit(ThreadContext *tc, Tick delay);
 112 void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
 113 void resetstats(ThreadContext *tc, Tick delay, Tick period);
 114 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
 115 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
 116 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
 117 void debugbreak(ThreadContext *tc);
 118 void switchcpu(ThreadContext *tc);
 119 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
 120 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
 121 void m5Syscall(ThreadContext *tc);
 122 void togglesync(ThreadContext *tc);
 123
 124 /**
 125  * Execute a decoded M5 pseudo instruction
 126  *
 127  * The ISA-specific code is responsible to decode the pseudo inst
 128  * function number and subfunction number. After that has been done,
 129  * the rest of the instruction can be implemented in an ISA-agnostic
 130  * manner using the ISA-specific getArguments functions.
 131  *
 132  * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
 133  * @param result A reference to a uint64_t to store a result in.
 134  * @return Whether the pseudo instruction was recognized/handled.
 135  */
 136
 137 template <typename ABI>
 138 bool
 139 pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
 140 {
 141     DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
 142
 143     result = 0;
 144
 145     switch (func) {
 146       case M5OP_ARM:
 147         invokeSimcall<ABI>(tc, arm);
 148         return true;
 149
 150       case M5OP_QUIESCE:
 151         invokeSimcall<ABI>(tc, quiesce);
 152         return true;
 153
 154       case M5OP_QUIESCE_NS:
 155         invokeSimcall<ABI>(tc, quiesceNs);
 156         return true;
 157
 158       case M5OP_QUIESCE_CYCLE:
 159         invokeSimcall<ABI>(tc, quiesceCycles);
 160         return true;
 161
 162       case M5OP_QUIESCE_TIME:
 163         result = invokeSimcall<ABI>(tc, quiesceTime);
 164         return true;
 165
 166       case M5OP_RPNS:
 167         result = invokeSimcall<ABI>(tc, rpns);
 168         return true;
 169
 170       case M5OP_WAKE_CPU:
 171         invokeSimcall<ABI>(tc, wakeCPU);
 172         return true;
 173
 174       case M5OP_EXIT:
 175         invokeSimcall<ABI>(tc, m5exit);
 176         return true;
 177
 178       case M5OP_FAIL:
 179         invokeSimcall<ABI>(tc, m5fail);
 180         return true;
 181
 182       case M5OP_INIT_PARAM:
 183         result = invokeSimcall<ABI>(tc, initParam);
 184         return true;
 185
 186       case M5OP_LOAD_SYMBOL:
 187         invokeSimcall<ABI>(tc, loadsymbol);
 188         return true;
 189
 190       case M5OP_RESET_STATS:
 191         invokeSimcall<ABI>(tc, resetstats);
 192         return true;
 193
 194       case M5OP_DUMP_STATS:
 195         invokeSimcall<ABI>(tc, dumpstats);
 196         return true;
 197
 198       case M5OP_DUMP_RESET_STATS:
 199         invokeSimcall<ABI>(tc, dumpresetstats);
 200         return true;
 201
 202       case M5OP_CHECKPOINT:
 203         invokeSimcall<ABI>(tc, m5checkpoint);
 204         return true;
 205
 206       case M5OP_WRITE_FILE:
 207         result = invokeSimcall<ABI>(tc, writefile);
 208         return true;
 209
 210       case M5OP_READ_FILE:
 211         result = invokeSimcall<ABI>(tc, readfile);
 212         return true;
 213
 214       case M5OP_DEBUG_BREAK:
 215         invokeSimcall<ABI>(tc, debugbreak);
 216         return true;
 217
 218       case M5OP_SWITCH_CPU:
 219         invokeSimcall<ABI>(tc, switchcpu);
 220         return true;
 221
 222       case M5OP_ADD_SYMBOL:
 223         invokeSimcall<ABI>(tc, addsymbol);
 224         return true;
 225
 226       case M5OP_PANIC:
 227         panic("M5 panic instruction called at %s\n", tc->pcState());
 228
 229       case M5OP_WORK_BEGIN:
 230         invokeSimcall<ABI>(tc, workbegin);
 231         return true;
 232
 233       case M5OP_WORK_END:
 234         invokeSimcall<ABI>(tc, workend);
 235         return true;
 236
 237       case M5OP_RESERVED1:
 238       case M5OP_RESERVED2:
 239       case M5OP_RESERVED3:
 240       case M5OP_RESERVED4:
 241       case M5OP_RESERVED5:
 242         warn("Unimplemented m5 op (%#x)\n", func);
 243         return false;
 244
 245       /* SE mode functions */
 246       case M5OP_SE_SYSCALL:
 247         invokeSimcall<ABI>(tc, m5Syscall);
 248         return true;
 249
 250       case M5OP_SE_PAGE_FAULT:
 251         invokeSimcall<ABI>(tc, TheISA::m5PageFault);
 252         return true;
 253
 254       /* dist-gem5 functions */
 255       case M5OP_DIST_TOGGLE_SYNC:
 256         invokeSimcall<ABI>(tc, togglesync);
 257         return true;
 258
 259       default:
 260         warn("Unhandled m5 op: %#x\n", func);
 261         return false;
 262     }
 263 }
 264
 265 } // namespace PseudoInst
 266
 267 #endif // __SIM_PSEUDO_INST_HH__