2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2010 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Steve Reinhardt
35 #include "base/callback.hh"
36 #include "base/inifile.hh"
37 #include "base/match.hh"
38 #include "base/misc.hh"
39 #include "base/trace.hh"
40 #include "base/types.hh"
41 #include "debug/Checkpoint.hh"
42 #include "sim/sim_object.hh"
43 #include "sim/stats.hh"
48 ////////////////////////////////////////////////////////////////////////
50 // SimObject member definitions
52 ////////////////////////////////////////////////////////////////////////
55 // static list of all SimObjects, used for initialization etc.
57 SimObject::SimObjectList
SimObject::simObjectList
;
60 // SimObject constructor: used to maintain static simObjectList
62 SimObject::SimObject(const Params
*p
)
63 : EventManager(p
->eventq
), _params(p
)
69 simObjectList
.push_back(this);
79 SimObject::loadState(Checkpoint
*cp
)
81 if (cp
->sectionExists(name())) {
82 DPRINTF(Checkpoint
, "unserializing\n");
83 unserialize(cp
, name());
85 DPRINTF(Checkpoint
, "no checkpoint section found\n");
90 SimObject::initState()
100 // no default statistics, so nothing to do in base implementation
103 SimObject::regStats()
108 SimObject::regFormulas()
113 SimObject::resetStats()
118 // static function: serialize all SimObjects.
121 SimObject::serializeAll(ostream
&os
)
123 SimObjectList::reverse_iterator ri
= simObjectList
.rbegin();
124 SimObjectList::reverse_iterator rend
= simObjectList
.rend();
126 for (; ri
!= rend
; ++ri
) {
127 SimObject
*obj
= *ri
;
136 // static function: flag which objects should have the debugger break
139 SimObject::debugObjectBreak(const string
&objs
)
141 SimObjectList::const_iterator i
= simObjectList
.begin();
142 SimObjectList::const_iterator end
= simObjectList
.end();
144 ObjectMatch
match(objs
);
145 for (; i
!= end
; ++i
) {
147 obj
->doDebugBreak
= match
.match(obj
->name());
152 debugObjectBreak(const char *objs
)
154 SimObject::debugObjectBreak(string(objs
));
159 SimObject::drain(Event
*drain_event
)
172 SimObject::setMemoryMode(State new_mode
)
174 panic("setMemoryMode() should only be called on systems");
178 SimObject::switchOut()
180 panic("Unimplemented!");
184 SimObject::takeOverFrom(BaseCPU
*cpu
)
186 panic("Unimplemented!");
191 SimObject::find(const char *name
)
193 SimObjectList::const_iterator i
= simObjectList
.begin();
194 SimObjectList::const_iterator end
= simObjectList
.end();
196 for (; i
!= end
; ++i
) {
198 if (obj
->name() == name
)