src/sim/sim_object.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #include <assert.h>
  33
  34 #include "base/callback.hh"
  35 #include "base/inifile.hh"
  36 #include "base/match.hh"
  37 #include "base/misc.hh"
  38 #include "base/trace.hh"
  39 #include "base/stats/events.hh"
  40 #include "base/serializer.hh"
  41 #include "sim/host.hh"
  42 #include "sim/sim_object.hh"
  43 #include "sim/stats.hh"
  44 #include "sim/param.hh"
  45
  46 using namespace std;
  47
  48
  49 ////////////////////////////////////////////////////////////////////////
  50 //
  51 // SimObject member definitions
  52 //
  53 ////////////////////////////////////////////////////////////////////////
  54
  55 //
  56 // static list of all SimObjects, used for initialization etc.
  57 //
  58 SimObject::SimObjectList SimObject::simObjectList;
  59
  60 namespace Stats {
  61     extern ObjectMatch event_ignore;
  62 }
  63
  64 //
  65 // SimObject constructor: used to maintain static simObjectList
  66 //
  67 SimObject::SimObject(Params *p)
  68     : _params(p)
  69 {
  70 #ifdef DEBUG
  71     doDebugBreak = false;
  72 #endif
  73
  74     doRecordEvent = !Stats::event_ignore.match(name());
  75     simObjectList.push_back(this);
  76     state = Atomic;
  77 }
  78
  79 //
  80 // SimObject constructor: used to maintain static simObjectList
  81 //
  82 SimObject::SimObject(const string &_name)
  83     : _params(new Params)
  84 {
  85     _params->name = _name;
  86 #ifdef DEBUG
  87     doDebugBreak = false;
  88 #endif
  89
  90     doRecordEvent = !Stats::event_ignore.match(name());
  91     simObjectList.push_back(this);
  92     state = Atomic;
  93 }
  94
  95 void
  96 SimObject::connect()
  97 {
  98 }
  99
 100 void
 101 SimObject::init()
 102 {
 103 }
 104
 105 //
 106 // no default statistics, so nothing to do in base implementation
 107 //
 108 void
 109 SimObject::regStats()
 110 {
 111 }
 112
 113 void
 114 SimObject::regFormulas()
 115 {
 116 }
 117
 118 void
 119 SimObject::resetStats()
 120 {
 121 }
 122
 123 //
 124 // static function:
 125 //   call regStats() on all SimObjects and then regFormulas() on all
 126 //   SimObjects.
 127 //
 128 struct SimObjectResetCB : public Callback
 129 {
 130     virtual void process() { SimObject::resetAllStats(); }
 131 };
 132
 133 namespace {
 134     static SimObjectResetCB StatResetCB;
 135 }
 136
 137 void
 138 SimObject::regAllStats()
 139 {
 140     SimObjectList::iterator i;
 141     SimObjectList::iterator end = simObjectList.end();
 142
 143     /**
 144      * @todo change cprintfs to DPRINTFs
 145      */
 146     for (i = simObjectList.begin(); i != end; ++i) {
 147 #ifdef STAT_DEBUG
 148         cprintf("registering stats for %s\n", (*i)->name());
 149 #endif
 150         (*i)->regStats();
 151     }
 152
 153     for (i = simObjectList.begin(); i != end; ++i) {
 154 #ifdef STAT_DEBUG
 155         cprintf("registering formulas for %s\n", (*i)->name());
 156 #endif
 157         (*i)->regFormulas();
 158     }
 159
 160     Stats::registerResetCallback(&StatResetCB);
 161 }
 162
 163 //
 164 // static function: call connect() on all SimObjects.
 165 //
 166 void
 167 SimObject::connectAll()
 168 {
 169     SimObjectList::iterator i = simObjectList.begin();
 170     SimObjectList::iterator end = simObjectList.end();
 171
 172     for (; i != end; ++i) {
 173         SimObject *obj = *i;
 174         obj->connect();
 175     }
 176 }
 177
 178 //
 179 // static function: call init() on all SimObjects.
 180 //
 181 void
 182 SimObject::initAll()
 183 {
 184     SimObjectList::iterator i = simObjectList.begin();
 185     SimObjectList::iterator end = simObjectList.end();
 186
 187     for (; i != end; ++i) {
 188         SimObject *obj = *i;
 189         obj->init();
 190     }
 191 }
 192
 193 //
 194 // static function: call resetStats() on all SimObjects.
 195 //
 196 void
 197 SimObject::resetAllStats()
 198 {
 199     SimObjectList::iterator i = simObjectList.begin();
 200     SimObjectList::iterator end = simObjectList.end();
 201
 202     for (; i != end; ++i) {
 203         SimObject *obj = *i;
 204         obj->resetStats();
 205     }
 206 }
 207
 208 //
 209 // static function: serialize all SimObjects.
 210 //
 211 void
 212 SimObject::serializeAll(ostream &os)
 213 {
 214     SimObjectList::reverse_iterator ri = simObjectList.rbegin();
 215     SimObjectList::reverse_iterator rend = simObjectList.rend();
 216
 217     for (; ri != rend; ++ri) {
 218         SimObject *obj = *ri;
 219         obj->nameOut(os);
 220         obj->serialize(os);
 221    }
 222 }
 223
 224 void
 225 SimObject::unserializeAll(Checkpoint *cp)
 226 {
 227     SimObjectList::reverse_iterator ri = simObjectList.rbegin();
 228     SimObjectList::reverse_iterator rend = simObjectList.rend();
 229
 230     for (; ri != rend; ++ri) {
 231         SimObject *obj = *ri;
 232         DPRINTFR(Config, "Unserializing '%s'\n",
 233                  obj->name());
 234         if(cp->sectionExists(obj->name()))
 235             obj->unserialize(cp, obj->name());
 236         else
 237             warn("Not unserializing '%s': no section found in checkpoint.\n",
 238                  obj->name());
 239    }
 240 }
 241
 242 #ifdef DEBUG
 243 //
 244 // static function: flag which objects should have the debugger break
 245 //
 246 void
 247 SimObject::debugObjectBreak(const string &objs)
 248 {
 249     SimObjectList::const_iterator i = simObjectList.begin();
 250     SimObjectList::const_iterator end = simObjectList.end();
 251
 252     ObjectMatch match(objs);
 253     for (; i != end; ++i) {
 254         SimObject *obj = *i;
 255         obj->doDebugBreak = match.match(obj->name());
 256    }
 257 }
 258
 259 void
 260 debugObjectBreak(const char *objs)
 261 {
 262     SimObject::debugObjectBreak(string(objs));
 263 }
 264 #endif
 265
 266 void
 267 SimObject::recordEvent(const std::string &stat)
 268 {
 269     if (doRecordEvent)
 270         Stats::recordEvent(stat);
 271 }
 272
 273 bool
 274 SimObject::quiesce(Event *quiesce_event)
 275 {
 276     if (state != QuiescedAtomic && state != Atomic) {
 277         panic("Must implement your own quiesce function if it is to be used "
 278               "in timing mode!");
 279     }
 280     state = QuiescedAtomic;
 281     return false;
 282 }
 283
 284 void
 285 SimObject::resume()
 286 {
 287     if (state == QuiescedAtomic) {
 288         state = Atomic;
 289     } else if (state == QuiescedTiming) {
 290         state = Timing;
 291     }
 292 }
 293
 294 void
 295 SimObject::setMemoryMode(State new_mode)
 296 {
 297     assert(new_mode == Timing || new_mode == Atomic);
 298     if (state == QuiescedAtomic && new_mode == Timing) {
 299         state = QuiescedTiming;
 300     } else if (state == QuiescedTiming && new_mode == Atomic) {
 301         state = QuiescedAtomic;
 302     } else {
 303         state = new_mode;
 304     }
 305 }
 306
 307 void
 308 SimObject::switchOut()
 309 {
 310     panic("Unimplemented!");
 311 }
 312
 313 void
 314 SimObject::takeOverFrom(BaseCPU *cpu)
 315 {
 316     panic("Unimplemented!");
 317 }
 318
 319 DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject)