sim: Expose the system's byte order as a param
[gem5.git] / src / sim / sim_object.hh
1 /*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 /* @file
43 * User Console Definitions
44 */
45
46 #ifndef __SIM_OBJECT_HH__
47 #define __SIM_OBJECT_HH__
48
49 #include <string>
50 #include <vector>
51
52 #include "base/stats/group.hh"
53 #include "params/SimObject.hh"
54 #include "sim/drain.hh"
55 #include "sim/eventq.hh"
56 #include "sim/port.hh"
57 #include "sim/serialize.hh"
58
59 class EventManager;
60 class ProbeManager;
61
62 /**
63 * Abstract superclass for simulation objects. Represents things that
64 * correspond to physical components and can be specified via the
65 * config file (CPUs, caches, etc.).
66 *
67 * SimObject initialization is controlled by the instantiate method in
68 * src/python/m5/simulate.py. There are slightly different
69 * initialization paths when starting the simulation afresh and when
70 * loading from a checkpoint. After instantiation and connecting
71 * ports, simulate.py initializes the object using the following call
72 * sequence:
73 *
74 * <ol>
75 * <li>SimObject::init()
76 * <li>SimObject::regStats()
77 * <li><ul>
78 * <li>SimObject::initState() if starting afresh.
79 * <li>SimObject::loadState() if restoring from a checkpoint.
80 * </ul>
81 * <li>SimObject::resetStats()
82 * <li>SimObject::startup()
83 * <li>Drainable::drainResume() if resuming from a checkpoint.
84 * </ol>
85 *
86 * @note Whenever a method is called on all objects in the simulator's
87 * object tree (e.g., init(), startup(), or loadState()), a pre-order
88 * depth-first traversal is performed (see descendants() in
89 * SimObject.py). This has the effect of calling the method on the
90 * parent node <i>before</i> its children.
91 */
92 class SimObject : public EventManager, public Serializable, public Drainable,
93 public Stats::Group
94 {
95 private:
96 typedef std::vector<SimObject *> SimObjectList;
97
98 /** List of all instantiated simulation objects. */
99 static SimObjectList simObjectList;
100
101 /** Manager coordinates hooking up probe points with listeners. */
102 ProbeManager *probeManager;
103
104 protected:
105 /**
106 * Cached copy of the object parameters.
107 *
108 * @ingroup api_simobject
109 */
110 const SimObjectParams *_params;
111
112 public:
113 typedef SimObjectParams Params;
114 /**
115 * @ingroup api_simobject
116 * @{
117 */
118 const Params *params() const { return _params; }
119 SimObject(const Params *_params);
120 /** @}*/ //end of the api_simobject group
121 virtual ~SimObject();
122
123 public:
124
125 /**
126 * @ingroup api_simobject
127 */
128 virtual const std::string name() const { return params()->name; }
129
130 /**
131 * init() is called after all C++ SimObjects have been created and
132 * all ports are connected. Initializations that are independent
133 * of unserialization but rely on a fully instantiated and
134 * connected SimObject graph should be done here.
135 *
136 * @ingroup api_simobject
137 */
138 virtual void init();
139
140 /**
141 * loadState() is called on each SimObject when restoring from a
142 * checkpoint. The default implementation simply calls
143 * unserialize() if there is a corresponding section in the
144 * checkpoint. However, objects can override loadState() to get
145 * other behaviors, e.g., doing other programmed initializations
146 * after unserialize(), or complaining if no checkpoint section is
147 * found.
148 *
149 * @param cp Checkpoint to restore the state from.
150 *
151 * @ingroup api_serialize
152 */
153 virtual void loadState(CheckpointIn &cp);
154
155 /**
156 * initState() is called on each SimObject when *not* restoring
157 * from a checkpoint. This provides a hook for state
158 * initializations that are only required for a "cold start".
159 *
160 * @ingroup api_serialize
161 */
162 virtual void initState();
163
164 /**
165 * Register probe points for this object.
166 *
167 * @ingroup api_simobject
168 */
169 virtual void regProbePoints();
170
171 /**
172 * Register probe listeners for this object.
173 *
174 * @ingroup api_simobject
175 */
176 virtual void regProbeListeners();
177
178 /**
179 * Get the probe manager for this object.
180 *
181 * @ingroup api_simobject
182 */
183 ProbeManager *getProbeManager();
184
185 /**
186 * Get a port with a given name and index. This is used at binding time
187 * and returns a reference to a protocol-agnostic port.
188 *
189 * @param if_name Port name
190 * @param idx Index in the case of a VectorPort
191 *
192 * @return A reference to the given port
193 *
194 * @ingroup api_simobject
195 */
196 virtual Port &getPort(const std::string &if_name,
197 PortID idx=InvalidPortID);
198
199 /**
200 * startup() is the final initialization call before simulation.
201 * All state is initialized (including unserialized state, if any,
202 * such as the curTick() value), so this is the appropriate place to
203 * schedule initial event(s) for objects that need them.
204 *
205 * @ingroup api_simobject
206 */
207 virtual void startup();
208
209 /**
210 * Provide a default implementation of the drain interface for
211 * objects that don't need draining.
212 */
213 DrainState drain() override { return DrainState::Drained; }
214
215 /**
216 * Write back dirty buffers to memory using functional writes.
217 *
218 * After returning, an object implementing this method should have
219 * written all its dirty data back to memory. This method is
220 * typically used to prepare a system with caches for
221 * checkpointing.
222 *
223 * @ingroup api_simobject
224 */
225 virtual void memWriteback() {};
226
227 /**
228 * Invalidate the contents of memory buffers.
229 *
230 * When the switching to hardware virtualized CPU models, we need
231 * to make sure that we don't have any cached state in the system
232 * that might become stale when we return. This method is used to
233 * flush all such state back to main memory.
234 *
235 * @warn This does <i>not</i> cause any dirty state to be written
236 * back to memory.
237 *
238 * @ingroup api_simobject
239 */
240 virtual void memInvalidate() {};
241
242 void serialize(CheckpointOut &cp) const override {};
243 void unserialize(CheckpointIn &cp) override {};
244
245 /**
246 * Serialize all SimObjects in the system.
247 */
248 static void serializeAll(CheckpointOut &cp);
249
250 #ifdef DEBUG
251 public:
252 bool doDebugBreak;
253 static void debugObjectBreak(const std::string &objs);
254 #endif
255
256 /**
257 * Find the SimObject with the given name and return a pointer to
258 * it. Primarily used for interactive debugging. Argument is
259 * char* rather than std::string to make it callable from gdb.
260 *
261 * @ingroup api_simobject
262 */
263 static SimObject *find(const char *name);
264 };
265
266 /**
267 * Base class to wrap object resolving functionality.
268 *
269 * This can be provided to the serialization framework to allow it to
270 * map object names onto C++ objects.
271 */
272 class SimObjectResolver
273 {
274 public:
275 virtual ~SimObjectResolver() { }
276
277 /**
278 * Find a SimObject given a full path name
279 *
280 * @ingroup api_serialize
281 */
282 virtual SimObject *resolveSimObject(const std::string &name) = 0;
283 };
284
285 #ifdef DEBUG
286 void debugObjectBreak(const char *objs);
287 #endif
288
289 #endif // __SIM_OBJECT_HH__