Merge with head, hopefully the last time for this batch.
[gem5.git] / src / sim / sim_object.hh
1 /*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 * Nathan Binkert
31 */
32
33 /* @file
34 * User Console Definitions
35 */
36
37 #ifndef __SIM_OBJECT_HH__
38 #define __SIM_OBJECT_HH__
39
40 #include <iostream>
41 #include <list>
42 #include <map>
43 #include <string>
44 #include <vector>
45
46 #include "enums/MemoryMode.hh"
47 #include "params/SimObject.hh"
48 #include "sim/eventq.hh"
49 #include "sim/serialize.hh"
50
51 class BaseCPU;
52 class Event;
53
54 /*
55 * Abstract superclass for simulation objects. Represents things that
56 * correspond to physical components and can be specified via the
57 * config file (CPUs, caches, etc.).
58 */
59 class SimObject : public EventManager, public Serializable
60 {
61 public:
62 enum State {
63 Running,
64 Draining,
65 Drained
66 };
67
68 private:
69 State state;
70
71 protected:
72 void changeState(State new_state) { state = new_state; }
73
74 public:
75 State getState() { return state; }
76
77 private:
78 typedef std::vector<SimObject *> SimObjectList;
79
80 // list of all instantiated simulation objects
81 static SimObjectList simObjectList;
82
83 protected:
84 const SimObjectParams *_params;
85
86 public:
87 typedef SimObjectParams Params;
88 const Params *params() const { return _params; }
89 SimObject(const Params *_params);
90 virtual ~SimObject() {}
91
92 public:
93
94 virtual const std::string name() const { return params()->name; }
95
96 // The following SimObject initialization methods are called from
97 // the instantiate() method in src/python/m5/simulate.py. See
98 // that function for details on how/when these methods are
99 // invoked.
100
101 /**
102 * init() is called after all C++ SimObjects have been created and
103 * all ports are connected. Initializations that are independent
104 * of unserialization but rely on a fully instantiated and
105 * connected SimObject graph should be done here.
106 */
107 virtual void init();
108
109 /**
110 * loadState() is called on each SimObject when restoring from a
111 * checkpoint. The default implementation simply calls
112 * unserialize() if there is a corresponding section in the
113 * checkpoint. However, objects can override loadState() to get
114 * other behaviors, e.g., doing other programmed initializations
115 * after unserialize(), or complaining if no checkpoint section is
116 * found.
117 */
118 virtual void loadState(Checkpoint *cp);
119
120 /**
121 * initState() is called on each SimObject when *not* restoring
122 * from a checkpoint. This provides a hook for state
123 * initializations that are only required for a "cold start".
124 */
125 virtual void initState();
126
127 // register statistics for this object
128 virtual void regStats();
129 virtual void regFormulas();
130 virtual void resetStats();
131
132 /**
133 * startup() is the final initialization call before simulation.
134 * All state is initialized (including unserialized state, if any,
135 * such as the curTick() value), so this is the appropriate place to
136 * schedule initial event(s) for objects that need them.
137 */
138 virtual void startup();
139
140 // static: call nameOut() & serialize() on all SimObjects
141 static void serializeAll(std::ostream &);
142
143 // Methods to drain objects in order to take checkpoints
144 // Or switch from timing -> atomic memory model
145 // Drain returns 0 if the simobject can drain immediately or
146 // the number of times the drain_event's process function will be called
147 // before the object will be done draining. Normally this should be 1
148 virtual unsigned int drain(Event *drain_event);
149 virtual void resume();
150 virtual void setMemoryMode(Enums::MemoryMode new_mode);
151 virtual void switchOut();
152 virtual void takeOverFrom(BaseCPU *cpu);
153
154 #ifdef DEBUG
155 public:
156 bool doDebugBreak;
157 static void debugObjectBreak(const std::string &objs);
158 #endif
159
160 /**
161 * Find the SimObject with the given name and return a pointer to
162 * it. Primarily used for interactive debugging. Argument is
163 * char* rather than std::string to make it callable from gdb.
164 */
165 static SimObject *find(const char *name);
166 };
167
168 #endif // __SIM_OBJECT_HH__