Merge zizzer:/bk/newmem
[gem5.git] / src / sim / sim_object.hh
1 /*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32 /* @file
33 * User Console Definitions
34 */
35
36 #ifndef __SIM_OBJECT_HH__
37 #define __SIM_OBJECT_HH__
38
39 #include <map>
40 #include <list>
41 #include <vector>
42 #include <iostream>
43
44 #include "sim/serialize.hh"
45 #include "sim/startup.hh"
46
47 class Serializer;
48
49 /*
50 * Abstract superclass for simulation objects. Represents things that
51 * correspond to physical components and can be specified via the
52 * config file (CPUs, caches, etc.).
53 */
54 class SimObject : public Serializable, protected StartupCallback
55 {
56 public:
57 struct Params {
58 std::string name;
59 };
60
61 protected:
62 Params *_params;
63
64 public:
65 const Params *params() const { return _params; }
66
67 private:
68 friend class Serializer;
69
70 typedef std::vector<SimObject *> SimObjectList;
71
72 // list of all instantiated simulation objects
73 static SimObjectList simObjectList;
74
75 public:
76 SimObject(Params *_params);
77 SimObject(const std::string &_name);
78
79 virtual ~SimObject() {}
80
81 virtual const std::string name() const { return params()->name; }
82
83 // initialization pass of all objects.
84 // Gets invoked after construction, before unserialize.
85 virtual void init();
86 virtual void connect();
87 static void initAll();
88 static void connectAll();
89
90 // register statistics for this object
91 virtual void regStats();
92 virtual void regFormulas();
93 virtual void resetStats();
94
95 // static: call reg_stats on all SimObjects
96 static void regAllStats();
97
98 // static: call resetStats on all SimObjects
99 static void resetAllStats();
100
101 // static: call nameOut() & serialize() on all SimObjects
102 static void serializeAll(std::ostream &);
103
104 // Methods to drain objects in order to take checkpoints
105 // Or switch from timing -> atomic memory model
106 virtual void drain(Serializer *serializer);
107 virtual void resume() { return;} ;
108 virtual void serializationComplete()
109 { assert(0 && "Unimplemented"); };
110
111 #ifdef DEBUG
112 public:
113 bool doDebugBreak;
114 static void debugObjectBreak(const std::string &objs);
115 #endif
116
117 public:
118 bool doRecordEvent;
119 void recordEvent(const std::string &stat);
120 };
121
122 #endif // __SIM_OBJECT_HH__