src/sim/stat_control.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * Copyright (c) 2013 Mark D. Hill and David A. Wood
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are
  21  * met: redistributions of source code must retain the above copyright
  22  * notice, this list of conditions and the following disclaimer;
  23  * redistributions in binary form must reproduce the above copyright
  24  * notice, this list of conditions and the following disclaimer in the
  25  * documentation and/or other materials provided with the distribution;
  26  * neither the name of the copyright holders nor the names of its
  27  * contributors may be used to endorse or promote products derived from
  28  * this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  */
  42
  43 // This file will contain default statistics for the simulator that
  44 // don't really belong to a specific simulator object
  45
  46 #include "sim/stat_control.hh"
  47
  48 #include <fstream>
  49 #include <iostream>
  50 #include <list>
  51
  52 #include "base/callback.hh"
  53 #include "base/hostinfo.hh"
  54 #include "base/statistics.hh"
  55 #include "base/time.hh"
  56 #include "cpu/base.hh"
  57 #include "sim/global_event.hh"
  58
  59 using namespace std;
  60
  61 Stats::Formula simSeconds;
  62 Stats::Value simTicks;
  63 Stats::Value finalTick;
  64 Stats::Value simFreq;
  65
  66 namespace Stats {
  67
  68 Time statTime(true);
  69 Tick startTick;
  70
  71 GlobalEvent *dumpEvent;
  72
  73 struct SimTicksReset : public Callback
  74 {
  75     void process()
  76     {
  77         statTime.setTimer();
  78         startTick = curTick();
  79     }
  80 };
  81
  82 double
  83 statElapsedTime()
  84 {
  85     Time now;
  86     now.setTimer();
  87
  88     Time elapsed = now - statTime;
  89     return elapsed;
  90 }
  91
  92 Tick
  93 statElapsedTicks()
  94 {
  95     return curTick() - startTick;
  96 }
  97
  98 Tick
  99 statFinalTick()
 100 {
 101     return curTick();
 102 }
 103
 104 SimTicksReset simTicksReset;
 105
 106 struct Global
 107 {
 108     Stats::Formula hostInstRate;
 109     Stats::Formula hostOpRate;
 110     Stats::Formula hostTickRate;
 111     Stats::Value hostMemory;
 112     Stats::Value hostSeconds;
 113
 114     Stats::Value simInsts;
 115     Stats::Value simOps;
 116
 117     Global();
 118 };
 119
 120 Global::Global()
 121 {
 122     simInsts
 123         .functor(BaseCPU::numSimulatedInsts)
 124         .name("sim_insts")
 125         .desc("Number of instructions simulated")
 126         .precision(0)
 127         .prereq(simInsts)
 128         ;
 129
 130     simOps
 131         .functor(BaseCPU::numSimulatedOps)
 132         .name("sim_ops")
 133         .desc("Number of ops (including micro ops) simulated")
 134         .precision(0)
 135         .prereq(simOps)
 136         ;
 137
 138     simSeconds
 139         .name("sim_seconds")
 140         .desc("Number of seconds simulated")
 141         ;
 142
 143     simFreq
 144         .scalar(SimClock::Frequency)
 145         .name("sim_freq")
 146         .desc("Frequency of simulated ticks")
 147         ;
 148
 149     simTicks
 150         .functor(statElapsedTicks)
 151         .name("sim_ticks")
 152         .desc("Number of ticks simulated")
 153         ;
 154
 155     finalTick
 156         .functor(statFinalTick)
 157         .name("final_tick")
 158         .desc("Number of ticks from beginning of simulation "
 159               "(restored from checkpoints and never reset)")
 160         ;
 161
 162     hostInstRate
 163         .name("host_inst_rate")
 164         .desc("Simulator instruction rate (inst/s)")
 165         .precision(0)
 166         .prereq(simInsts)
 167         ;
 168
 169     hostOpRate
 170         .name("host_op_rate")
 171         .desc("Simulator op (including micro ops) rate (op/s)")
 172         .precision(0)
 173         .prereq(simOps)
 174         ;
 175
 176     hostMemory
 177         .functor(memUsage)
 178         .name("host_mem_usage")
 179         .desc("Number of bytes of host memory used")
 180         .prereq(hostMemory)
 181         ;
 182
 183     hostSeconds
 184         .functor(statElapsedTime)
 185         .name("host_seconds")
 186         .desc("Real time elapsed on the host")
 187         .precision(2)
 188         ;
 189
 190     hostTickRate
 191         .name("host_tick_rate")
 192         .desc("Simulator tick rate (ticks/s)")
 193         .precision(0)
 194         ;
 195
 196     simSeconds = simTicks / simFreq;
 197     hostInstRate = simInsts / hostSeconds;
 198     hostOpRate = simOps / hostSeconds;
 199     hostTickRate = simTicks / hostSeconds;
 200
 201     registerResetCallback(&simTicksReset);
 202 }
 203
 204 void
 205 initSimStats()
 206 {
 207     static Global global;
 208 }
 209
 210 /**
 211  * Event to dump and/or reset the statistics.
 212  */
 213 class StatEvent : public GlobalEvent
 214 {
 215   private:
 216     bool dump;
 217     bool reset;
 218     Tick repeat;
 219
 220   public:
 221     StatEvent(Tick _when, bool _dump, bool _reset, Tick _repeat)
 222         : GlobalEvent(_when, Stat_Event_Pri, 0),
 223           dump(_dump), reset(_reset), repeat(_repeat)
 224     {
 225     }
 226
 227     virtual void
 228     process()
 229     {
 230         if (dump)
 231             Stats::dump();
 232
 233         if (reset)
 234             Stats::reset();
 235
 236         if (repeat) {
 237             Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat);
 238         }
 239     }
 240
 241     const char *description() const { return "GlobalStatEvent"; }
 242 };
 243
 244 void
 245 schedStatEvent(bool dump, bool reset, Tick when, Tick repeat)
 246 {
 247     // simQuantum is being added to the time when the stats would be
 248     // dumped so as to ensure that this event happens only after the next
 249     // sync amongst the event queues.  Asingle event queue simulation
 250     // should remain unaffected.
 251     dumpEvent = new StatEvent(when + simQuantum, dump, reset, repeat);
 252 }
 253
 254 void
 255 periodicStatDump(Tick period)
 256 {
 257     /*
 258      * If the period is set to 0, then we do not want to dump periodically,
 259      * thus we deschedule the event. Else, if the period is not 0, but the event
 260      * has already been scheduled, we need to get rid of the old event before we
 261      * create a new one, as the old event will no longer be moved forward in the
 262      * event that we resume from a checkpoint.
 263      */
 264     if (dumpEvent != NULL && (period == 0 || dumpEvent->scheduled())) {
 265         // Event should AutoDelete, so we do not need to free it.
 266         dumpEvent->deschedule();
 267     }
 268
 269     /*
 270      * If the period is not 0, we schedule the event. If this is called with a
 271      * period that is less than the current tick, then we shift the first dump
 272      * by curTick. This ensures that we do not schedule the event is the past.
 273      */
 274     if (period != 0) {
 275         // Schedule the event
 276         if (period >= curTick()) {
 277             schedStatEvent(true, true, (Tick)period, (Tick)period);
 278         } else {
 279             schedStatEvent(true, true, (Tick)period + curTick(), (Tick)period);
 280         }
 281     }
 282 }
 283
 284 void
 285 updateEvents()
 286 {
 287     /*
 288      * If the dumpEvent has been scheduled, but is scheduled in the past, then
 289      * we need to shift the event to be at a valid point in time. Therefore, we
 290      * shift the event by curTick.
 291      */
 292     if (dumpEvent != NULL &&
 293         (dumpEvent->scheduled() && dumpEvent->when() < curTick())) {
 294         // shift by curTick() and reschedule
 295         Tick _when = dumpEvent->when();
 296         dumpEvent->reschedule(_when + curTick());
 297     }
 298 }
 299
 300 } // namespace Stats