2 * Copyright (c) 2011-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
48 #include "arch/remote_gdb.hh"
49 #include "arch/utility.hh"
50 #include "base/loader/object_file.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/str.hh"
53 #include "base/trace.hh"
54 #include "cpu/thread_context.hh"
55 #include "debug/Loader.hh"
56 #include "debug/WorkItems.hh"
57 #include "mem/abstract_mem.hh"
58 #include "mem/physical.hh"
59 #include "params/System.hh"
60 #include "sim/byteswap.hh"
61 #include "sim/debug.hh"
62 #include "sim/full_system.hh"
63 #include "sim/system.hh"
66 * To avoid linking errors with LTO, only include the header if we
67 * actually have a definition.
69 #if THE_ISA != NULL_ISA
70 #include "kern/kernel_stats.hh"
74 using namespace TheISA
;
76 vector
<System
*> System::systemList
;
78 int System::numSystemsRunning
= 0;
80 System::System(Params
*p
)
81 : MemObject(p
), _systemPort("system_port", this),
84 init_param(p
->init_param
),
85 physProxy(_systemPort
, p
->cache_line_size
),
86 kernelSymtab(nullptr),
88 loadAddrMask(p
->load_addr_mask
),
89 loadAddrOffset(p
->load_offset
),
91 physmem(name() + ".physmem", p
->memories
),
92 memoryMode(p
->mem_mode
),
93 _cacheLineSize(p
->cache_line_size
),
96 numWorkIds(p
->num_work_ids
),
99 instEventQueue("system instruction-based event queue")
101 // add self to global system list
102 systemList
.push_back(this);
105 kernelSymtab
= new SymbolTable
;
106 if (!debugSymbolTable
)
107 debugSymbolTable
= new SymbolTable
;
110 // check if the cache line size is a value known to work
111 if (!(_cacheLineSize
== 16 || _cacheLineSize
== 32 ||
112 _cacheLineSize
== 64 || _cacheLineSize
== 128))
113 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
115 // Get the generic system master IDs
116 MasterID tmp_id M5_VAR_USED
;
117 tmp_id
= getMasterId("writebacks");
118 assert(tmp_id
== Request::wbMasterId
);
119 tmp_id
= getMasterId("functional");
120 assert(tmp_id
== Request::funcMasterId
);
121 tmp_id
= getMasterId("interrupt");
122 assert(tmp_id
== Request::intMasterId
);
125 if (params()->kernel
== "") {
126 inform("No kernel set for full system simulation. "
127 "Assuming you know what you're doing\n");
129 // Get the kernel code
130 kernel
= createObjectFile(params()->kernel
);
131 inform("kernel located at: %s", params()->kernel
);
134 fatal("Could not load kernel file %s", params()->kernel
);
136 // setup entry points
137 kernelStart
= kernel
->textBase();
138 kernelEnd
= kernel
->bssBase() + kernel
->bssSize();
139 kernelEntry
= kernel
->entryPoint();
142 if (!kernel
->loadGlobalSymbols(kernelSymtab
))
143 fatal("could not load kernel symbols\n");
145 if (!kernel
->loadLocalSymbols(kernelSymtab
))
146 fatal("could not load kernel local symbols\n");
148 if (!kernel
->loadGlobalSymbols(debugSymbolTable
))
149 fatal("could not load kernel symbols\n");
151 if (!kernel
->loadLocalSymbols(debugSymbolTable
))
152 fatal("could not load kernel local symbols\n");
154 // Loading only needs to happen once and after memory system is
155 // connected so it will happen in initState()
159 // increment the number of running systms
162 // Set back pointers to the system in all memories
163 for (int x
= 0; x
< params()->memories
.size(); x
++)
164 params()->memories
[x
]->system(this);
172 for (uint32_t j
= 0; j
< numWorkIds
; j
++)
173 delete workItemStats
[j
];
179 // check that the system port is connected
180 if (!_systemPort
.isConnected())
181 panic("System port on %s is not connected.\n", name());
185 System::getMasterPort(const std::string
&if_name
, PortID idx
)
187 // no need to distinguish at the moment (besides checking)
192 System::setMemoryMode(Enums::MemoryMode mode
)
194 assert(getDrainState() == Drainable::Drained
);
198 bool System::breakpoint()
200 if (remoteGDB
.size())
201 return remoteGDB
[0]->breakpoint();
206 * Setting rgdb_wait to a positive integer waits for a remote debugger to
207 * connect to that context ID before continuing. This should really
208 be a parameter on the CPU object or something...
213 System::registerThreadContext(ThreadContext
*tc
, int assigned
)
216 if (assigned
== -1) {
217 for (id
= 0; id
< threadContexts
.size(); id
++) {
218 if (!threadContexts
[id
])
222 if (threadContexts
.size() <= id
)
223 threadContexts
.resize(id
+ 1);
225 if (threadContexts
.size() <= assigned
)
226 threadContexts
.resize(assigned
+ 1);
230 if (threadContexts
[id
])
231 fatal("Cannot have two CPUs with the same id (%d)\n", id
);
233 threadContexts
[id
] = tc
;
236 #if THE_ISA != NULL_ISA
237 int port
= getRemoteGDBPort();
239 RemoteGDB
*rgdb
= new RemoteGDB(this, tc
);
240 GDBListener
*gdbl
= new GDBListener(rgdb
, port
+ id
);
243 if (rgdb_wait
!= -1 && rgdb_wait
== id
)
246 if (remoteGDB
.size() <= id
) {
247 remoteGDB
.resize(id
+ 1);
250 remoteGDB
[id
] = rgdb
;
254 activeCpus
.push_back(false);
260 System::numRunningContexts()
263 for (int i
= 0; i
< _numContexts
; ++i
) {
264 if (threadContexts
[i
]->status() != ThreadContext::Halted
)
274 for (int i
= 0; i
< threadContexts
.size(); i
++)
275 TheISA::startupCPU(threadContexts
[i
], i
);
276 // Moved from the constructor to here since it relies on the
277 // address map being resolved in the interconnect
279 * Load the kernel code into memory
281 if (params()->kernel
!= "") {
282 if (params()->kernel_addr_check
) {
283 // Validate kernel mapping before loading binary
284 if (!(isMemAddr((kernelStart
& loadAddrMask
) +
286 isMemAddr((kernelEnd
& loadAddrMask
) +
288 fatal("Kernel is mapped to invalid location (not memory). "
289 "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
291 kernelEnd
, (kernelStart
& loadAddrMask
) +
293 (kernelEnd
& loadAddrMask
) + loadAddrOffset
);
296 // Load program sections into memory
297 kernel
->loadSections(physProxy
, loadAddrMask
, loadAddrOffset
);
299 DPRINTF(Loader
, "Kernel start = %#x\n", kernelStart
);
300 DPRINTF(Loader
, "Kernel end = %#x\n", kernelEnd
);
301 DPRINTF(Loader
, "Kernel entry = %#x\n", kernelEntry
);
302 DPRINTF(Loader
, "Kernel loaded...\n");
310 System::replaceThreadContext(ThreadContext
*tc
, int context_id
)
312 if (context_id
>= threadContexts
.size()) {
313 panic("replaceThreadContext: bad id, %d >= %d\n",
314 context_id
, threadContexts
.size());
317 threadContexts
[context_id
] = tc
;
318 if (context_id
< remoteGDB
.size())
319 remoteGDB
[context_id
]->replaceThreadContext(tc
);
323 System::allocPhysPages(int npages
)
325 Addr return_addr
= pagePtr
<< PageShift
;
328 Addr next_return_addr
= pagePtr
<< PageShift
;
330 AddrRange
m5opRange(0xffff0000, 0xffffffff);
331 if (m5opRange
.contains(next_return_addr
)) {
332 warn("Reached m5ops MMIO region\n");
333 return_addr
= 0xffffffff;
334 pagePtr
= 0xffffffff >> PageShift
;
337 if ((pagePtr
<< PageShift
) > physmem
.totalSize())
338 fatal("Out of memory, please increase size of physical memory.");
343 System::memSize() const
345 return physmem
.totalSize();
349 System::freeMemSize() const
351 return physmem
.totalSize() - (pagePtr
<< PageShift
);
355 System::isMemAddr(Addr addr
) const
357 return physmem
.isMemAddr(addr
);
361 System::drain(DrainManager
*dm
)
363 setDrainState(Drainable::Drained
);
368 System::drainResume()
370 Drainable::drainResume();
375 System::serialize(ostream
&os
)
378 kernelSymtab
->serialize("kernel_symtab", os
);
379 SERIALIZE_SCALAR(pagePtr
);
380 SERIALIZE_SCALAR(nextPID
);
383 // also serialize the memories in the system
384 nameOut(os
, csprintf("%s.physmem", name()));
385 physmem
.serialize(os
);
390 System::unserialize(Checkpoint
*cp
, const string
§ion
)
393 kernelSymtab
->unserialize("kernel_symtab", cp
, section
);
394 UNSERIALIZE_SCALAR(pagePtr
);
395 UNSERIALIZE_SCALAR(nextPID
);
396 unserializeSymtab(cp
, section
);
398 // also unserialize the memories in the system
399 physmem
.unserialize(cp
, csprintf("%s.physmem", name()));
405 for (uint32_t j
= 0; j
< numWorkIds
; j
++) {
406 workItemStats
[j
] = new Stats::Histogram();
407 stringstream namestr
;
408 ccprintf(namestr
, "work_item_type%d", j
);
409 workItemStats
[j
]->init(20)
410 .name(name() + "." + namestr
.str())
411 .desc("Run time stat for" + namestr
.str())
412 .prereq(*workItemStats
[j
]);
417 System::workItemEnd(uint32_t tid
, uint32_t workid
)
419 std::pair
<uint32_t,uint32_t> p(tid
, workid
);
420 if (!lastWorkItemStarted
.count(p
))
423 Tick samp
= curTick() - lastWorkItemStarted
[p
];
424 DPRINTF(WorkItems
, "Work item end: %d\t%d\t%lld\n", tid
, workid
, samp
);
426 if (workid
>= numWorkIds
)
427 fatal("Got workid greater than specified in system configuration\n");
429 workItemStats
[workid
]->sample(samp
);
430 lastWorkItemStarted
.erase(p
);
434 System::printSystems()
436 ios::fmtflags
flags(cerr
.flags());
438 vector
<System
*>::iterator i
= systemList
.begin();
439 vector
<System
*>::iterator end
= systemList
.end();
440 for (; i
!= end
; ++i
) {
442 cerr
<< "System " << sys
->name() << ": " << hex
<< sys
<< endl
;
451 System::printSystems();
455 System::getMasterId(std::string master_name
)
457 // strip off system name if the string starts with it
458 if (startswith(master_name
, name()))
459 master_name
= master_name
.erase(0, name().size() + 1);
461 // CPUs in switch_cpus ask for ids again after switching
462 for (int i
= 0; i
< masterIds
.size(); i
++) {
463 if (masterIds
[i
] == master_name
) {
468 // Verify that the statistics haven't been enabled yet
469 // Otherwise objects will have sized their stat buckets and
470 // they will be too small
472 if (Stats::enabled()) {
473 fatal("Can't request a masterId after regStats(). "
474 "You must do so in init().\n");
477 masterIds
.push_back(master_name
);
479 return masterIds
.size() - 1;
483 System::getMasterName(MasterID master_id
)
485 if (master_id
>= masterIds
.size())
486 fatal("Invalid master_id passed to getMasterName()\n");
488 return masterIds
[master_id
];
492 SystemParams::create()
494 return new System(this);