2 * Copyright (c) 2011-2014,2017-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
48 #include "sim/system.hh"
52 #include "arch/remote_gdb.hh"
53 #include "arch/utility.hh"
54 #include "base/loader/object_file.hh"
55 #include "base/loader/symtab.hh"
56 #include "base/str.hh"
57 #include "base/trace.hh"
58 #include "config/use_kvm.hh"
60 #include "cpu/kvm/base.hh"
61 #include "cpu/kvm/vm.hh"
63 #include "cpu/base.hh"
64 #include "cpu/thread_context.hh"
65 #include "debug/Loader.hh"
66 #include "debug/WorkItems.hh"
67 #include "mem/abstract_mem.hh"
68 #include "mem/physical.hh"
69 #include "params/System.hh"
70 #include "sim/byteswap.hh"
71 #include "sim/debug.hh"
72 #include "sim/full_system.hh"
73 #include "sim/redirect_path.hh"
76 * To avoid linking errors with LTO, only include the header if we
77 * actually have a definition.
79 #if THE_ISA != NULL_ISA
80 #include "kern/kernel_stats.hh"
85 using namespace TheISA
;
87 vector
<System
*> System::systemList
;
89 int System::numSystemsRunning
= 0;
91 System::System(Params
*p
)
92 : SimObject(p
), _systemPort("system_port", this),
93 multiThread(p
->multi_thread
),
95 init_param(p
->init_param
),
96 physProxy(_systemPort
, p
->cache_line_size
),
97 kernelSymtab(nullptr),
99 loadAddrMask(p
->load_addr_mask
),
100 loadAddrOffset(p
->load_offset
),
106 physmem(name() + ".physmem", p
->memories
, p
->mmap_using_noreserve
),
107 memoryMode(p
->mem_mode
),
108 _cacheLineSize(p
->cache_line_size
),
111 numWorkIds(p
->num_work_ids
),
112 thermalModel(p
->thermal_model
),
115 redirectPaths(p
->redirect_paths
)
118 // add self to global system list
119 systemList
.push_back(this);
123 kvmVM
->setSystem(this);
128 kernelSymtab
= new SymbolTable
;
129 if (!debugSymbolTable
)
130 debugSymbolTable
= new SymbolTable
;
133 // check if the cache line size is a value known to work
134 if (!(_cacheLineSize
== 16 || _cacheLineSize
== 32 ||
135 _cacheLineSize
== 64 || _cacheLineSize
== 128))
136 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
138 // Get the generic system master IDs
139 MasterID tmp_id M5_VAR_USED
;
140 tmp_id
= getMasterId(this, "writebacks");
141 assert(tmp_id
== Request::wbMasterId
);
142 tmp_id
= getMasterId(this, "functional");
143 assert(tmp_id
== Request::funcMasterId
);
144 tmp_id
= getMasterId(this, "interrupt");
145 assert(tmp_id
== Request::intMasterId
);
148 if (params()->kernel
== "") {
149 inform("No kernel set for full system simulation. "
150 "Assuming you know what you're doing\n");
152 // Get the kernel code
153 kernel
= createObjectFile(params()->kernel
);
154 inform("kernel located at: %s", params()->kernel
);
157 fatal("Could not load kernel file %s", params()->kernel
);
159 kernelImage
= kernel
->buildImage();
161 // setup entry points
162 kernelStart
= kernelImage
.minAddr();
163 kernelEnd
= kernelImage
.maxAddr();
164 kernelEntry
= kernel
->entryPoint();
166 // If load_addr_mask is set to 0x0, then auto-calculate
167 // the smallest mask to cover all kernel addresses so gem5
168 // can relocate the kernel to a new offset.
169 if (loadAddrMask
== 0) {
170 Addr shift_amt
= findMsbSet(kernelEnd
- kernelStart
) + 1;
171 loadAddrMask
= ((Addr
)1 << shift_amt
) - 1;
174 kernelImage
.move([this](Addr a
) {
175 return (a
& loadAddrMask
) + loadAddrOffset
;
179 if (!kernel
->loadGlobalSymbols(kernelSymtab
))
180 fatal("could not load kernel symbols\n");
182 if (!kernel
->loadLocalSymbols(kernelSymtab
))
183 fatal("could not load kernel local symbols\n");
185 if (!kernel
->loadGlobalSymbols(debugSymbolTable
))
186 fatal("could not load kernel symbols\n");
188 if (!kernel
->loadLocalSymbols(debugSymbolTable
))
189 fatal("could not load kernel local symbols\n");
191 // Loading only needs to happen once and after memory system is
192 // connected so it will happen in initState()
195 for (const auto &obj_name
: p
->kernel_extras
) {
196 inform("Loading additional kernel object: %s", obj_name
);
197 ObjectFile
*obj
= createObjectFile(obj_name
);
198 fatal_if(!obj
, "Failed to additional kernel object '%s'.\n",
200 kernelExtras
.push_back(obj
);
204 // increment the number of running systems
207 // Set back pointers to the system in all memories
208 for (int x
= 0; x
< params()->memories
.size(); x
++)
209 params()->memories
[x
]->system(this);
217 for (uint32_t j
= 0; j
< numWorkIds
; j
++)
218 delete workItemStats
[j
];
224 // check that the system port is connected
225 if (!_systemPort
.isConnected())
226 panic("System port on %s is not connected.\n", name());
230 System::getPort(const std::string
&if_name
, PortID idx
)
232 // no need to distinguish at the moment (besides checking)
237 System::setMemoryMode(Enums::MemoryMode mode
)
239 assert(drainState() == DrainState::Drained
);
243 bool System::breakpoint()
245 if (remoteGDB
.size())
246 return remoteGDB
[0]->breakpoint();
251 System::registerThreadContext(ThreadContext
*tc
, ContextID assigned
)
254 if (id
== InvalidContextID
) {
255 // Find an unused context ID for this thread.
257 while (id
< threadContexts
.size() && threadContexts
[id
])
261 if (threadContexts
.size() <= id
)
262 threadContexts
.resize(id
+ 1);
264 fatal_if(threadContexts
[id
],
265 "Cannot have two CPUs with the same id (%d)\n", id
);
267 threadContexts
[id
] = tc
;
269 #if THE_ISA != NULL_ISA
270 int port
= getRemoteGDBPort();
272 RemoteGDB
*rgdb
= new RemoteGDB(this, tc
, port
+ id
);
275 BaseCPU
*cpu
= tc
->getCpuPtr();
276 if (cpu
->waitForRemoteGDB()) {
277 inform("%s: Waiting for a remote GDB connection on port %d.\n",
278 cpu
->name(), rgdb
->port());
282 if (remoteGDB
.size() <= id
) {
283 remoteGDB
.resize(id
+ 1);
286 remoteGDB
[id
] = rgdb
;
290 activeCpus
.push_back(false);
296 System::numRunningContexts()
298 return std::count_if(
299 threadContexts
.cbegin(),
300 threadContexts
.cend(),
301 [] (ThreadContext
* tc
) {
302 return ((tc
->status() != ThreadContext::Halted
) &&
303 (tc
->status() != ThreadContext::Halting
));
312 for (int i
= 0; i
< threadContexts
.size(); i
++)
313 TheISA::startupCPU(threadContexts
[i
], i
);
314 // Moved from the constructor to here since it relies on the
315 // address map being resolved in the interconnect
317 * Load the kernel code into memory
319 auto mapper
= [this](Addr a
) {
320 return (a
& loadAddrMask
) + loadAddrOffset
;
322 if (params()->kernel
!= "") {
323 if (params()->kernel_addr_check
) {
324 // Validate kernel mapping before loading binary
325 if (!isMemAddr(mapper(kernelStart
)) ||
326 !isMemAddr(mapper(kernelEnd
))) {
327 fatal("Kernel is mapped to invalid location (not memory). "
328 "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
329 kernelStart
, kernelEnd
,
330 mapper(kernelStart
), mapper(kernelEnd
));
333 // Load program sections into memory
334 kernelImage
.write(physProxy
);
335 for (const auto &extra_kernel
: kernelExtras
)
336 extra_kernel
->buildImage().move(mapper
).write(physProxy
);
338 DPRINTF(Loader
, "Kernel start = %#x\n", kernelStart
);
339 DPRINTF(Loader
, "Kernel end = %#x\n", kernelEnd
);
340 DPRINTF(Loader
, "Kernel entry = %#x\n", kernelEntry
);
341 DPRINTF(Loader
, "Kernel loaded...\n");
347 System::replaceThreadContext(ThreadContext
*tc
, ContextID context_id
)
349 if (context_id
>= threadContexts
.size()) {
350 panic("replaceThreadContext: bad id, %d >= %d\n",
351 context_id
, threadContexts
.size());
354 threadContexts
[context_id
] = tc
;
355 if (context_id
< remoteGDB
.size())
356 remoteGDB
[context_id
]->replaceThreadContext(tc
);
360 System::validKvmEnvironment() const
363 if (threadContexts
.empty())
366 for (auto tc
: threadContexts
) {
367 if (dynamic_cast<BaseKvmCPU
*>(tc
->getCpuPtr()) == nullptr) {
378 System::allocPhysPages(int npages
)
380 Addr return_addr
= pagePtr
<< PageShift
;
383 Addr next_return_addr
= pagePtr
<< PageShift
;
385 AddrRange
m5opRange(0xffff0000, 0xffffffff);
386 if (m5opRange
.contains(next_return_addr
)) {
387 warn("Reached m5ops MMIO region\n");
388 return_addr
= 0xffffffff;
389 pagePtr
= 0xffffffff >> PageShift
;
392 if ((pagePtr
<< PageShift
) > physmem
.totalSize())
393 fatal("Out of memory, please increase size of physical memory.");
398 System::memSize() const
400 return physmem
.totalSize();
404 System::freeMemSize() const
406 return physmem
.totalSize() - (pagePtr
<< PageShift
);
410 System::isMemAddr(Addr addr
) const
412 return physmem
.isMemAddr(addr
);
416 System::drainResume()
422 System::serialize(CheckpointOut
&cp
) const
425 kernelSymtab
->serialize("kernel_symtab", cp
);
426 SERIALIZE_SCALAR(pagePtr
);
429 // also serialize the memories in the system
430 physmem
.serializeSection(cp
, "physmem");
435 System::unserialize(CheckpointIn
&cp
)
438 kernelSymtab
->unserialize("kernel_symtab", cp
);
439 UNSERIALIZE_SCALAR(pagePtr
);
440 unserializeSymtab(cp
);
442 // also unserialize the memories in the system
443 physmem
.unserializeSection(cp
, "physmem");
449 SimObject::regStats();
451 for (uint32_t j
= 0; j
< numWorkIds
; j
++) {
452 workItemStats
[j
] = new Stats::Histogram();
453 stringstream namestr
;
454 ccprintf(namestr
, "work_item_type%d", j
);
455 workItemStats
[j
]->init(20)
456 .name(name() + "." + namestr
.str())
457 .desc("Run time stat for" + namestr
.str())
458 .prereq(*workItemStats
[j
]);
463 System::workItemEnd(uint32_t tid
, uint32_t workid
)
465 std::pair
<uint32_t,uint32_t> p(tid
, workid
);
466 if (!lastWorkItemStarted
.count(p
))
469 Tick samp
= curTick() - lastWorkItemStarted
[p
];
470 DPRINTF(WorkItems
, "Work item end: %d\t%d\t%lld\n", tid
, workid
, samp
);
472 if (workid
>= numWorkIds
)
473 fatal("Got workid greater than specified in system configuration\n");
475 workItemStats
[workid
]->sample(samp
);
476 lastWorkItemStarted
.erase(p
);
480 System::printSystems()
482 ios::fmtflags
flags(cerr
.flags());
484 vector
<System
*>::iterator i
= systemList
.begin();
485 vector
<System
*>::iterator end
= systemList
.end();
486 for (; i
!= end
; ++i
) {
488 cerr
<< "System " << sys
->name() << ": " << hex
<< sys
<< endl
;
497 System::printSystems();
501 System::stripSystemName(const std::string
& master_name
) const
503 if (startswith(master_name
, name())) {
504 return master_name
.substr(name().size());
511 System::lookupMasterId(const SimObject
* obj
) const
513 MasterID id
= Request::invldMasterId
;
515 // number of occurrences of the SimObject pointer
516 // in the master list.
519 for (int i
= 0; i
< masters
.size(); i
++) {
520 if (masters
[i
].obj
== obj
) {
526 fatal_if(obj_number
> 1,
527 "Cannot lookup MasterID by SimObject pointer: "
528 "More than one master is sharing the same SimObject\n");
534 System::lookupMasterId(const std::string
& master_name
) const
536 std::string name
= stripSystemName(master_name
);
538 for (int i
= 0; i
< masters
.size(); i
++) {
539 if (masters
[i
].masterName
== name
) {
544 return Request::invldMasterId
;
548 System::getGlobalMasterId(const std::string
& master_name
)
550 return _getMasterId(nullptr, master_name
);
554 System::getMasterId(const SimObject
* master
, std::string submaster
)
556 auto master_name
= leafMasterName(master
, submaster
);
557 return _getMasterId(master
, master_name
);
561 System::_getMasterId(const SimObject
* master
, const std::string
& master_name
)
563 std::string name
= stripSystemName(master_name
);
565 // CPUs in switch_cpus ask for ids again after switching
566 for (int i
= 0; i
< masters
.size(); i
++) {
567 if (masters
[i
].masterName
== name
) {
572 // Verify that the statistics haven't been enabled yet
573 // Otherwise objects will have sized their stat buckets and
574 // they will be too small
576 if (Stats::enabled()) {
577 fatal("Can't request a masterId after regStats(). "
578 "You must do so in init().\n");
581 // Generate a new MasterID incrementally
582 MasterID master_id
= masters
.size();
584 // Append the new Master metadata to the group of system Masters.
585 masters
.emplace_back(master
, name
, master_id
);
587 return masters
.back().masterId
;
591 System::leafMasterName(const SimObject
* master
, const std::string
& submaster
)
593 if (submaster
.empty()) {
594 return master
->name();
596 // Get the full master name by appending the submaster name to
597 // the root SimObject master name
598 return master
->name() + "." + submaster
;
603 System::getMasterName(MasterID master_id
)
605 if (master_id
>= masters
.size())
606 fatal("Invalid master_id passed to getMasterName()\n");
608 const auto& master_info
= masters
[master_id
];
609 return master_info
.masterName
;
613 SystemParams::create()
615 return new System(this);