src/sim/system.cc

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2006 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Lisa Hsu
  43  *          Nathan Binkert
  44  *          Ali Saidi
  45  *          Rick Strong
  46  */
  47
  48 #include "arch/isa_traits.hh"
  49 #include "arch/remote_gdb.hh"
  50 #include "arch/utility.hh"
  51 #include "arch/vtophys.hh"
  52 #include "base/loader/object_file.hh"
  53 #include "base/loader/symtab.hh"
  54 #include "base/str.hh"
  55 #include "base/trace.hh"
  56 #include "config/the_isa.hh"
  57 #include "cpu/thread_context.hh"
  58 #include "debug/Loader.hh"
  59 #include "debug/WorkItems.hh"
  60 #include "kern/kernel_stats.hh"
  61 #include "mem/abstract_mem.hh"
  62 #include "mem/physical.hh"
  63 #include "params/System.hh"
  64 #include "sim/byteswap.hh"
  65 #include "sim/debug.hh"
  66 #include "sim/full_system.hh"
  67 #include "sim/system.hh"
  68
  69 using namespace std;
  70 using namespace TheISA;
  71
  72 vector<System *> System::systemList;
  73
  74 int System::numSystemsRunning = 0;
  75
  76 System::System(Params *p)
  77     : MemObject(p), _systemPort("system_port", this),
  78       _numContexts(0),
  79       pagePtr(0),
  80       init_param(p->init_param),
  81       physProxy(_systemPort),
  82       virtProxy(_systemPort),
  83       loadAddrMask(p->load_addr_mask),
  84       nextPID(0),
  85       physmem(name() + ".physmem", p->memories),
  86       memoryMode(p->mem_mode),
  87       workItemsBegin(0),
  88       workItemsEnd(0),
  89       numWorkIds(p->num_work_ids),
  90       _params(p),
  91       totalNumInsts(0),
  92       instEventQueue("system instruction-based event queue")
  93 {
  94     // add self to global system list
  95     systemList.push_back(this);
  96
  97     if (FullSystem) {
  98         kernelSymtab = new SymbolTable;
  99         if (!debugSymbolTable)
 100             debugSymbolTable = new SymbolTable;
 101     }
 102
 103     // Get the generic system master IDs
 104     MasterID tmp_id M5_VAR_USED;
 105     tmp_id = getMasterId("writebacks");
 106     assert(tmp_id == Request::wbMasterId);
 107     tmp_id = getMasterId("functional");
 108     assert(tmp_id == Request::funcMasterId);
 109     tmp_id = getMasterId("interrupt");
 110     assert(tmp_id == Request::intMasterId);
 111
 112     if (FullSystem) {
 113         if (params()->kernel == "") {
 114             inform("No kernel set for full system simulation. "
 115                    "Assuming you know what you're doing\n");
 116
 117             kernel = NULL;
 118         } else {
 119             // Get the kernel code
 120             kernel = createObjectFile(params()->kernel);
 121             inform("kernel located at: %s", params()->kernel);
 122
 123             if (kernel == NULL)
 124                 fatal("Could not load kernel file %s", params()->kernel);
 125
 126             // setup entry points
 127             kernelStart = kernel->textBase();
 128             kernelEnd = kernel->bssBase() + kernel->bssSize();
 129             kernelEntry = kernel->entryPoint();
 130
 131             // load symbols
 132             if (!kernel->loadGlobalSymbols(kernelSymtab))
 133                 fatal("could not load kernel symbols\n");
 134
 135             if (!kernel->loadLocalSymbols(kernelSymtab))
 136                 fatal("could not load kernel local symbols\n");
 137
 138             if (!kernel->loadGlobalSymbols(debugSymbolTable))
 139                 fatal("could not load kernel symbols\n");
 140
 141             if (!kernel->loadLocalSymbols(debugSymbolTable))
 142                 fatal("could not load kernel local symbols\n");
 143
 144             // Loading only needs to happen once and after memory system is
 145             // connected so it will happen in initState()
 146         }
 147     }
 148
 149     // increment the number of running systms
 150     numSystemsRunning++;
 151
 152     // Set back pointers to the system in all memories
 153     for (int x = 0; x < params()->memories.size(); x++)
 154         params()->memories[x]->system(this);
 155 }
 156
 157 System::~System()
 158 {
 159     delete kernelSymtab;
 160     delete kernel;
 161
 162     for (uint32_t j = 0; j < numWorkIds; j++)
 163         delete workItemStats[j];
 164 }
 165
 166 void
 167 System::init()
 168 {
 169     // check that the system port is connected
 170     if (!_systemPort.isConnected())
 171         panic("System port on %s is not connected.\n", name());
 172 }
 173
 174 BaseMasterPort&
 175 System::getMasterPort(const std::string &if_name, PortID idx)
 176 {
 177     // no need to distinguish at the moment (besides checking)
 178     return _systemPort;
 179 }
 180
 181 void
 182 System::setMemoryMode(Enums::MemoryMode mode)
 183 {
 184     assert(getState() == Drained);
 185     memoryMode = mode;
 186 }
 187
 188 bool System::breakpoint()
 189 {
 190     if (remoteGDB.size())
 191         return remoteGDB[0]->breakpoint();
 192     return false;
 193 }
 194
 195 /**
 196  * Setting rgdb_wait to a positive integer waits for a remote debugger to
 197  * connect to that context ID before continuing.  This should really
 198    be a parameter on the CPU object or something...
 199  */
 200 int rgdb_wait = -1;
 201
 202 int
 203 System::registerThreadContext(ThreadContext *tc, int assigned)
 204 {
 205     int id;
 206     if (assigned == -1) {
 207         for (id = 0; id < threadContexts.size(); id++) {
 208             if (!threadContexts[id])
 209                 break;
 210         }
 211
 212         if (threadContexts.size() <= id)
 213             threadContexts.resize(id + 1);
 214     } else {
 215         if (threadContexts.size() <= assigned)
 216             threadContexts.resize(assigned + 1);
 217         id = assigned;
 218     }
 219
 220     if (threadContexts[id])
 221         fatal("Cannot have two CPUs with the same id (%d)\n", id);
 222
 223     threadContexts[id] = tc;
 224     _numContexts++;
 225
 226     int port = getRemoteGDBPort();
 227     if (port) {
 228         RemoteGDB *rgdb = new RemoteGDB(this, tc);
 229         GDBListener *gdbl = new GDBListener(rgdb, port + id);
 230         gdbl->listen();
 231
 232         if (rgdb_wait != -1 && rgdb_wait == id)
 233             gdbl->accept();
 234
 235         if (remoteGDB.size() <= id) {
 236             remoteGDB.resize(id + 1);
 237         }
 238
 239         remoteGDB[id] = rgdb;
 240     }
 241
 242     activeCpus.push_back(false);
 243
 244     return id;
 245 }
 246
 247 int
 248 System::numRunningContexts()
 249 {
 250     int running = 0;
 251     for (int i = 0; i < _numContexts; ++i) {
 252         if (threadContexts[i]->status() != ThreadContext::Halted)
 253             ++running;
 254     }
 255     return running;
 256 }
 257
 258 void
 259 System::initState()
 260 {
 261     if (FullSystem) {
 262         for (int i = 0; i < threadContexts.size(); i++)
 263             TheISA::startupCPU(threadContexts[i], i);
 264         // Moved from the constructor to here since it relies on the
 265         // address map being resolved in the interconnect
 266         /**
 267          * Load the kernel code into memory
 268          */
 269         if (params()->kernel != "")  {
 270             // Validate kernel mapping before loading binary
 271             if (!(isMemAddr(kernelStart & loadAddrMask) &&
 272                             isMemAddr(kernelEnd & loadAddrMask))) {
 273                 fatal("Kernel is mapped to invalid location (not memory). "
 274                       "kernelStart 0x(%x) - kernelEnd 0x(%x)\n", kernelStart,
 275                       kernelEnd);
 276             }
 277             // Load program sections into memory
 278             kernel->loadSections(physProxy, loadAddrMask);
 279
 280             DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
 281             DPRINTF(Loader, "Kernel end   = %#x\n", kernelEnd);
 282             DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
 283             DPRINTF(Loader, "Kernel loaded...\n");
 284         }
 285     }
 286
 287     activeCpus.clear();
 288 }
 289
 290 void
 291 System::replaceThreadContext(ThreadContext *tc, int context_id)
 292 {
 293     if (context_id >= threadContexts.size()) {
 294         panic("replaceThreadContext: bad id, %d >= %d\n",
 295               context_id, threadContexts.size());
 296     }
 297
 298     threadContexts[context_id] = tc;
 299     if (context_id < remoteGDB.size())
 300         remoteGDB[context_id]->replaceThreadContext(tc);
 301 }
 302
 303 Addr
 304 System::allocPhysPages(int npages)
 305 {
 306     Addr return_addr = pagePtr << LogVMPageSize;
 307     pagePtr += npages;
 308     if ((pagePtr << LogVMPageSize) > physmem.totalSize())
 309         fatal("Out of memory, please increase size of physical memory.");
 310     return return_addr;
 311 }
 312
 313 Addr
 314 System::memSize() const
 315 {
 316     return physmem.totalSize();
 317 }
 318
 319 Addr
 320 System::freeMemSize() const
 321 {
 322    return physmem.totalSize() - (pagePtr << LogVMPageSize);
 323 }
 324
 325 bool
 326 System::isMemAddr(Addr addr) const
 327 {
 328     return physmem.isMemAddr(addr);
 329 }
 330
 331 void
 332 System::resume()
 333 {
 334     SimObject::resume();
 335     totalNumInsts = 0;
 336 }
 337
 338 void
 339 System::serialize(ostream &os)
 340 {
 341     if (FullSystem)
 342         kernelSymtab->serialize("kernel_symtab", os);
 343     SERIALIZE_SCALAR(pagePtr);
 344     SERIALIZE_SCALAR(nextPID);
 345     serializeSymtab(os);
 346
 347     // also serialize the memories in the system
 348     nameOut(os, csprintf("%s.physmem", name()));
 349     physmem.serialize(os);
 350 }
 351
 352
 353 void
 354 System::unserialize(Checkpoint *cp, const string &section)
 355 {
 356     if (FullSystem)
 357         kernelSymtab->unserialize("kernel_symtab", cp, section);
 358     UNSERIALIZE_SCALAR(pagePtr);
 359     UNSERIALIZE_SCALAR(nextPID);
 360     unserializeSymtab(cp, section);
 361
 362     // also unserialize the memories in the system
 363     physmem.unserialize(cp, csprintf("%s.physmem", name()));
 364 }
 365
 366 void
 367 System::regStats()
 368 {
 369     for (uint32_t j = 0; j < numWorkIds ; j++) {
 370         workItemStats[j] = new Stats::Histogram();
 371         stringstream namestr;
 372         ccprintf(namestr, "work_item_type%d", j);
 373         workItemStats[j]->init(20)
 374                          .name(name() + "." + namestr.str())
 375                          .desc("Run time stat for" + namestr.str())
 376                          .prereq(*workItemStats[j]);
 377     }
 378 }
 379
 380 void
 381 System::workItemEnd(uint32_t tid, uint32_t workid)
 382 {
 383     std::pair<uint32_t,uint32_t> p(tid, workid);
 384     if (!lastWorkItemStarted.count(p))
 385         return;
 386
 387     Tick samp = curTick() - lastWorkItemStarted[p];
 388     DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
 389
 390     if (workid >= numWorkIds)
 391         fatal("Got workid greater than specified in system configuration\n");
 392
 393     workItemStats[workid]->sample(samp);
 394     lastWorkItemStarted.erase(p);
 395 }
 396
 397 void
 398 System::printSystems()
 399 {
 400     vector<System *>::iterator i = systemList.begin();
 401     vector<System *>::iterator end = systemList.end();
 402     for (; i != end; ++i) {
 403         System *sys = *i;
 404         cerr << "System " << sys->name() << ": " << hex << sys << endl;
 405     }
 406 }
 407
 408 void
 409 printSystems()
 410 {
 411     System::printSystems();
 412 }
 413
 414 MasterID
 415 System::getMasterId(std::string master_name)
 416 {
 417     // strip off system name if the string starts with it
 418     if (startswith(master_name, name()))
 419         master_name = master_name.erase(0, name().size() + 1);
 420
 421     // CPUs in switch_cpus ask for ids again after switching
 422     for (int i = 0; i < masterIds.size(); i++) {
 423         if (masterIds[i] == master_name) {
 424             return i;
 425         }
 426     }
 427
 428     // Verify that the statistics haven't been enabled yet
 429     // Otherwise objects will have sized their stat buckets and
 430     // they will be too small
 431
 432     if (Stats::enabled())
 433         fatal("Can't request a masterId after regStats(). \
 434                 You must do so in init().\n");
 435
 436     masterIds.push_back(master_name);
 437
 438     return masterIds.size() - 1;
 439 }
 440
 441 std::string
 442 System::getMasterName(MasterID master_id)
 443 {
 444     if (master_id >= masterIds.size())
 445         fatal("Invalid master_id passed to getMasterName()\n");
 446
 447     return masterIds[master_id];
 448 }
 449
 450 const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
 451     "timing"};
 452
 453 System *
 454 SystemParams::create()
 455 {
 456     return new System(this);
 457 }