cpu: Change thread assignments for heterogenous SMT
[gem5.git] / src / sim / system.cc
1 /*
2 * Copyright (c) 2011-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Lisa Hsu
43 * Nathan Binkert
44 * Ali Saidi
45 * Rick Strong
46 */
47
48 #include "arch/remote_gdb.hh"
49 #include "arch/utility.hh"
50 #include "base/loader/object_file.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/str.hh"
53 #include "base/trace.hh"
54 #include "cpu/thread_context.hh"
55 #include "debug/Loader.hh"
56 #include "debug/WorkItems.hh"
57 #include "mem/abstract_mem.hh"
58 #include "mem/physical.hh"
59 #include "params/System.hh"
60 #include "sim/byteswap.hh"
61 #include "sim/debug.hh"
62 #include "sim/full_system.hh"
63 #include "sim/system.hh"
64
65 /**
66 * To avoid linking errors with LTO, only include the header if we
67 * actually have a definition.
68 */
69 #if THE_ISA != NULL_ISA
70 #include "kern/kernel_stats.hh"
71 #endif
72
73 using namespace std;
74 using namespace TheISA;
75
76 vector<System *> System::systemList;
77
78 int System::numSystemsRunning = 0;
79
80 System::System(Params *p)
81 : MemObject(p), _systemPort("system_port", this),
82 _numContexts(0),
83 multiThread(p->multi_thread),
84 pagePtr(0),
85 init_param(p->init_param),
86 physProxy(_systemPort, p->cache_line_size),
87 kernelSymtab(nullptr),
88 kernel(nullptr),
89 loadAddrMask(p->load_addr_mask),
90 loadAddrOffset(p->load_offset),
91 nextPID(0),
92 physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
93 memoryMode(p->mem_mode),
94 _cacheLineSize(p->cache_line_size),
95 workItemsBegin(0),
96 workItemsEnd(0),
97 numWorkIds(p->num_work_ids),
98 _params(p),
99 totalNumInsts(0),
100 instEventQueue("system instruction-based event queue")
101 {
102 // add self to global system list
103 systemList.push_back(this);
104
105 if (FullSystem) {
106 kernelSymtab = new SymbolTable;
107 if (!debugSymbolTable)
108 debugSymbolTable = new SymbolTable;
109 }
110
111 // check if the cache line size is a value known to work
112 if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
113 _cacheLineSize == 64 || _cacheLineSize == 128))
114 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
115
116 // Get the generic system master IDs
117 MasterID tmp_id M5_VAR_USED;
118 tmp_id = getMasterId("writebacks");
119 assert(tmp_id == Request::wbMasterId);
120 tmp_id = getMasterId("functional");
121 assert(tmp_id == Request::funcMasterId);
122 tmp_id = getMasterId("interrupt");
123 assert(tmp_id == Request::intMasterId);
124
125 if (FullSystem) {
126 if (params()->kernel == "") {
127 inform("No kernel set for full system simulation. "
128 "Assuming you know what you're doing\n");
129 } else {
130 // Get the kernel code
131 kernel = createObjectFile(params()->kernel);
132 inform("kernel located at: %s", params()->kernel);
133
134 if (kernel == NULL)
135 fatal("Could not load kernel file %s", params()->kernel);
136
137 // setup entry points
138 kernelStart = kernel->textBase();
139 kernelEnd = kernel->bssBase() + kernel->bssSize();
140 kernelEntry = kernel->entryPoint();
141
142 // load symbols
143 if (!kernel->loadGlobalSymbols(kernelSymtab))
144 fatal("could not load kernel symbols\n");
145
146 if (!kernel->loadLocalSymbols(kernelSymtab))
147 fatal("could not load kernel local symbols\n");
148
149 if (!kernel->loadGlobalSymbols(debugSymbolTable))
150 fatal("could not load kernel symbols\n");
151
152 if (!kernel->loadLocalSymbols(debugSymbolTable))
153 fatal("could not load kernel local symbols\n");
154
155 // Loading only needs to happen once and after memory system is
156 // connected so it will happen in initState()
157 }
158 }
159
160 // increment the number of running systms
161 numSystemsRunning++;
162
163 // Set back pointers to the system in all memories
164 for (int x = 0; x < params()->memories.size(); x++)
165 params()->memories[x]->system(this);
166 }
167
168 System::~System()
169 {
170 delete kernelSymtab;
171 delete kernel;
172
173 for (uint32_t j = 0; j < numWorkIds; j++)
174 delete workItemStats[j];
175 }
176
177 void
178 System::init()
179 {
180 // check that the system port is connected
181 if (!_systemPort.isConnected())
182 panic("System port on %s is not connected.\n", name());
183 }
184
185 BaseMasterPort&
186 System::getMasterPort(const std::string &if_name, PortID idx)
187 {
188 // no need to distinguish at the moment (besides checking)
189 return _systemPort;
190 }
191
192 void
193 System::setMemoryMode(Enums::MemoryMode mode)
194 {
195 assert(drainState() == DrainState::Drained);
196 memoryMode = mode;
197 }
198
199 bool System::breakpoint()
200 {
201 if (remoteGDB.size())
202 return remoteGDB[0]->breakpoint();
203 return false;
204 }
205
206 /**
207 * Setting rgdb_wait to a positive integer waits for a remote debugger to
208 * connect to that context ID before continuing. This should really
209 be a parameter on the CPU object or something...
210 */
211 int rgdb_wait = -1;
212
213 ContextID
214 System::registerThreadContext(ThreadContext *tc, ContextID assigned)
215 {
216 int id;
217 if (assigned == InvalidContextID) {
218 for (id = 0; id < threadContexts.size(); id++) {
219 if (!threadContexts[id])
220 break;
221 }
222
223 if (threadContexts.size() <= id)
224 threadContexts.resize(id + 1);
225 } else {
226 if (threadContexts.size() <= assigned)
227 threadContexts.resize(assigned + 1);
228 id = assigned;
229 }
230
231 if (threadContexts[id])
232 fatal("Cannot have two CPUs with the same id (%d)\n", id);
233
234 threadContexts[id] = tc;
235 _numContexts++;
236
237 #if THE_ISA != NULL_ISA
238 int port = getRemoteGDBPort();
239 if (port) {
240 RemoteGDB *rgdb = new RemoteGDB(this, tc);
241 GDBListener *gdbl = new GDBListener(rgdb, port + id);
242 gdbl->listen();
243
244 if (rgdb_wait != -1 && rgdb_wait == id)
245 gdbl->accept();
246
247 if (remoteGDB.size() <= id) {
248 remoteGDB.resize(id + 1);
249 }
250
251 remoteGDB[id] = rgdb;
252 }
253 #endif
254
255 activeCpus.push_back(false);
256
257 return id;
258 }
259
260 int
261 System::numRunningContexts()
262 {
263 int running = 0;
264 for (int i = 0; i < _numContexts; ++i) {
265 if (threadContexts[i]->status() != ThreadContext::Halted)
266 ++running;
267 }
268 return running;
269 }
270
271 void
272 System::initState()
273 {
274 if (FullSystem) {
275 for (int i = 0; i < threadContexts.size(); i++)
276 TheISA::startupCPU(threadContexts[i], i);
277 // Moved from the constructor to here since it relies on the
278 // address map being resolved in the interconnect
279 /**
280 * Load the kernel code into memory
281 */
282 if (params()->kernel != "") {
283 if (params()->kernel_addr_check) {
284 // Validate kernel mapping before loading binary
285 if (!(isMemAddr((kernelStart & loadAddrMask) +
286 loadAddrOffset) &&
287 isMemAddr((kernelEnd & loadAddrMask) +
288 loadAddrOffset))) {
289 fatal("Kernel is mapped to invalid location (not memory). "
290 "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
291 kernelStart,
292 kernelEnd, (kernelStart & loadAddrMask) +
293 loadAddrOffset,
294 (kernelEnd & loadAddrMask) + loadAddrOffset);
295 }
296 }
297 // Load program sections into memory
298 kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset);
299
300 DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
301 DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd);
302 DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
303 DPRINTF(Loader, "Kernel loaded...\n");
304 }
305 }
306 }
307
308 void
309 System::replaceThreadContext(ThreadContext *tc, ContextID context_id)
310 {
311 if (context_id >= threadContexts.size()) {
312 panic("replaceThreadContext: bad id, %d >= %d\n",
313 context_id, threadContexts.size());
314 }
315
316 threadContexts[context_id] = tc;
317 if (context_id < remoteGDB.size())
318 remoteGDB[context_id]->replaceThreadContext(tc);
319 }
320
321 Addr
322 System::allocPhysPages(int npages)
323 {
324 Addr return_addr = pagePtr << PageShift;
325 pagePtr += npages;
326
327 Addr next_return_addr = pagePtr << PageShift;
328
329 AddrRange m5opRange(0xffff0000, 0xffffffff);
330 if (m5opRange.contains(next_return_addr)) {
331 warn("Reached m5ops MMIO region\n");
332 return_addr = 0xffffffff;
333 pagePtr = 0xffffffff >> PageShift;
334 }
335
336 if ((pagePtr << PageShift) > physmem.totalSize())
337 fatal("Out of memory, please increase size of physical memory.");
338 return return_addr;
339 }
340
341 Addr
342 System::memSize() const
343 {
344 return physmem.totalSize();
345 }
346
347 Addr
348 System::freeMemSize() const
349 {
350 return physmem.totalSize() - (pagePtr << PageShift);
351 }
352
353 bool
354 System::isMemAddr(Addr addr) const
355 {
356 return physmem.isMemAddr(addr);
357 }
358
359 void
360 System::drainResume()
361 {
362 totalNumInsts = 0;
363 }
364
365 void
366 System::serialize(CheckpointOut &cp) const
367 {
368 if (FullSystem)
369 kernelSymtab->serialize("kernel_symtab", cp);
370 SERIALIZE_SCALAR(pagePtr);
371 SERIALIZE_SCALAR(nextPID);
372 serializeSymtab(cp);
373
374 // also serialize the memories in the system
375 physmem.serializeSection(cp, "physmem");
376 }
377
378
379 void
380 System::unserialize(CheckpointIn &cp)
381 {
382 if (FullSystem)
383 kernelSymtab->unserialize("kernel_symtab", cp);
384 UNSERIALIZE_SCALAR(pagePtr);
385 UNSERIALIZE_SCALAR(nextPID);
386 unserializeSymtab(cp);
387
388 // also unserialize the memories in the system
389 physmem.unserializeSection(cp, "physmem");
390 }
391
392 void
393 System::regStats()
394 {
395 for (uint32_t j = 0; j < numWorkIds ; j++) {
396 workItemStats[j] = new Stats::Histogram();
397 stringstream namestr;
398 ccprintf(namestr, "work_item_type%d", j);
399 workItemStats[j]->init(20)
400 .name(name() + "." + namestr.str())
401 .desc("Run time stat for" + namestr.str())
402 .prereq(*workItemStats[j]);
403 }
404 }
405
406 void
407 System::workItemEnd(uint32_t tid, uint32_t workid)
408 {
409 std::pair<uint32_t,uint32_t> p(tid, workid);
410 if (!lastWorkItemStarted.count(p))
411 return;
412
413 Tick samp = curTick() - lastWorkItemStarted[p];
414 DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
415
416 if (workid >= numWorkIds)
417 fatal("Got workid greater than specified in system configuration\n");
418
419 workItemStats[workid]->sample(samp);
420 lastWorkItemStarted.erase(p);
421 }
422
423 void
424 System::printSystems()
425 {
426 ios::fmtflags flags(cerr.flags());
427
428 vector<System *>::iterator i = systemList.begin();
429 vector<System *>::iterator end = systemList.end();
430 for (; i != end; ++i) {
431 System *sys = *i;
432 cerr << "System " << sys->name() << ": " << hex << sys << endl;
433 }
434
435 cerr.flags(flags);
436 }
437
438 void
439 printSystems()
440 {
441 System::printSystems();
442 }
443
444 MasterID
445 System::getMasterId(std::string master_name)
446 {
447 // strip off system name if the string starts with it
448 if (startswith(master_name, name()))
449 master_name = master_name.erase(0, name().size() + 1);
450
451 // CPUs in switch_cpus ask for ids again after switching
452 for (int i = 0; i < masterIds.size(); i++) {
453 if (masterIds[i] == master_name) {
454 return i;
455 }
456 }
457
458 // Verify that the statistics haven't been enabled yet
459 // Otherwise objects will have sized their stat buckets and
460 // they will be too small
461
462 if (Stats::enabled()) {
463 fatal("Can't request a masterId after regStats(). "
464 "You must do so in init().\n");
465 }
466
467 masterIds.push_back(master_name);
468
469 return masterIds.size() - 1;
470 }
471
472 std::string
473 System::getMasterName(MasterID master_id)
474 {
475 if (master_id >= masterIds.size())
476 fatal("Invalid master_id passed to getMasterName()\n");
477
478 return masterIds[master_id];
479 }
480
481 System *
482 SystemParams::create()
483 {
484 return new System(this);
485 }