2 * Copyright (c) 2011-2014,2017-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
48 #include "sim/system.hh"
52 #include "arch/remote_gdb.hh"
53 #include "arch/utility.hh"
54 #include "base/loader/object_file.hh"
55 #include "base/loader/symtab.hh"
56 #include "base/str.hh"
57 #include "base/trace.hh"
58 #include "config/use_kvm.hh"
60 #include "cpu/kvm/base.hh"
61 #include "cpu/kvm/vm.hh"
63 #include "cpu/base.hh"
64 #include "cpu/thread_context.hh"
65 #include "debug/Loader.hh"
66 #include "debug/WorkItems.hh"
67 #include "mem/abstract_mem.hh"
68 #include "mem/physical.hh"
69 #include "params/System.hh"
70 #include "sim/byteswap.hh"
71 #include "sim/debug.hh"
72 #include "sim/full_system.hh"
73 #include "sim/redirect_path.hh"
76 * To avoid linking errors with LTO, only include the header if we
77 * actually have a definition.
79 #if THE_ISA != NULL_ISA
80 #include "kern/kernel_stats.hh"
85 using namespace TheISA
;
87 vector
<System
*> System::systemList
;
89 int System::numSystemsRunning
= 0;
91 System::System(Params
*p
)
92 : SimObject(p
), _systemPort("system_port", this),
93 multiThread(p
->multi_thread
),
95 init_param(p
->init_param
),
96 physProxy(_systemPort
, p
->cache_line_size
),
97 kernelSymtab(nullptr),
99 loadAddrMask(p
->load_addr_mask
),
100 loadAddrOffset(p
->load_offset
),
106 physmem(name() + ".physmem", p
->memories
, p
->mmap_using_noreserve
),
107 memoryMode(p
->mem_mode
),
108 _cacheLineSize(p
->cache_line_size
),
111 numWorkIds(p
->num_work_ids
),
112 thermalModel(p
->thermal_model
),
115 redirectPaths(p
->redirect_paths
)
118 // add self to global system list
119 systemList
.push_back(this);
123 kvmVM
->setSystem(this);
128 kernelSymtab
= new SymbolTable
;
129 if (!debugSymbolTable
)
130 debugSymbolTable
= new SymbolTable
;
133 // check if the cache line size is a value known to work
134 if (!(_cacheLineSize
== 16 || _cacheLineSize
== 32 ||
135 _cacheLineSize
== 64 || _cacheLineSize
== 128))
136 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
138 // Get the generic system master IDs
139 MasterID tmp_id M5_VAR_USED
;
140 tmp_id
= getMasterId(this, "writebacks");
141 assert(tmp_id
== Request::wbMasterId
);
142 tmp_id
= getMasterId(this, "functional");
143 assert(tmp_id
== Request::funcMasterId
);
144 tmp_id
= getMasterId(this, "interrupt");
145 assert(tmp_id
== Request::intMasterId
);
148 if (params()->kernel
== "") {
149 inform("No kernel set for full system simulation. "
150 "Assuming you know what you're doing\n");
152 // Get the kernel code
153 kernel
= createObjectFile(params()->kernel
);
154 inform("kernel located at: %s", params()->kernel
);
157 fatal("Could not load kernel file %s", params()->kernel
);
159 kernelImage
= kernel
->buildImage();
161 // setup entry points
162 kernelStart
= kernelImage
.minAddr();
163 kernelEnd
= kernelImage
.maxAddr();
164 kernelEntry
= kernel
->entryPoint();
166 // If load_addr_mask is set to 0x0, then auto-calculate
167 // the smallest mask to cover all kernel addresses so gem5
168 // can relocate the kernel to a new offset.
169 if (loadAddrMask
== 0) {
170 Addr shift_amt
= findMsbSet(kernelEnd
- kernelStart
) + 1;
171 loadAddrMask
= ((Addr
)1 << shift_amt
) - 1;
174 kernelImage
.move([this](Addr a
) {
175 return (a
& loadAddrMask
) + loadAddrOffset
;
179 if (!kernel
->loadGlobalSymbols(kernelSymtab
))
180 fatal("could not load kernel symbols\n");
182 if (!kernel
->loadLocalSymbols(kernelSymtab
))
183 fatal("could not load kernel local symbols\n");
185 if (!kernel
->loadGlobalSymbols(debugSymbolTable
))
186 fatal("could not load kernel symbols\n");
188 if (!kernel
->loadLocalSymbols(debugSymbolTable
))
189 fatal("could not load kernel local symbols\n");
191 // Loading only needs to happen once and after memory system is
192 // connected so it will happen in initState()
195 for (const auto &obj_name
: p
->kernel_extras
) {
196 inform("Loading additional kernel object: %s", obj_name
);
197 ObjectFile
*obj
= createObjectFile(obj_name
);
198 fatal_if(!obj
, "Failed to additional kernel object '%s'.\n",
200 kernelExtras
.push_back(obj
);
204 // increment the number of running systems
207 // Set back pointers to the system in all memories
208 for (int x
= 0; x
< params()->memories
.size(); x
++)
209 params()->memories
[x
]->system(this);
217 for (uint32_t j
= 0; j
< numWorkIds
; j
++)
218 delete workItemStats
[j
];
224 // check that the system port is connected
225 if (!_systemPort
.isConnected())
226 panic("System port on %s is not connected.\n", name());
230 System::getPort(const std::string
&if_name
, PortID idx
)
232 // no need to distinguish at the moment (besides checking)
237 System::setMemoryMode(Enums::MemoryMode mode
)
239 assert(drainState() == DrainState::Drained
);
243 bool System::breakpoint()
245 if (remoteGDB
.size())
246 return remoteGDB
[0]->breakpoint();
251 System::registerThreadContext(ThreadContext
*tc
, ContextID assigned
)
254 if (id
== InvalidContextID
) {
255 // Find an unused context ID for this thread.
257 while (id
< threadContexts
.size() && threadContexts
[id
])
261 if (threadContexts
.size() <= id
)
262 threadContexts
.resize(id
+ 1);
264 fatal_if(threadContexts
[id
],
265 "Cannot have two CPUs with the same id (%d)\n", id
);
267 threadContexts
[id
] = tc
;
268 for (auto *e
: liveEvents
)
271 #if THE_ISA != NULL_ISA
272 int port
= getRemoteGDBPort();
274 RemoteGDB
*rgdb
= new RemoteGDB(this, tc
, port
+ id
);
277 BaseCPU
*cpu
= tc
->getCpuPtr();
278 if (cpu
->waitForRemoteGDB()) {
279 inform("%s: Waiting for a remote GDB connection on port %d.\n",
280 cpu
->name(), rgdb
->port());
284 if (remoteGDB
.size() <= id
) {
285 remoteGDB
.resize(id
+ 1);
288 remoteGDB
[id
] = rgdb
;
292 activeCpus
.push_back(false);
298 System::schedule(PCEvent
*event
)
301 liveEvents
.push_back(event
);
302 for (auto *tc
: threadContexts
)
303 all
= tc
->schedule(event
) && all
;
308 System::remove(PCEvent
*event
)
311 liveEvents
.remove(event
);
312 for (auto *tc
: threadContexts
)
313 all
= tc
->remove(event
) && all
;
318 System::numRunningContexts()
320 return std::count_if(
321 threadContexts
.cbegin(),
322 threadContexts
.cend(),
323 [] (ThreadContext
* tc
) {
324 return ((tc
->status() != ThreadContext::Halted
) &&
325 (tc
->status() != ThreadContext::Halting
));
334 for (int i
= 0; i
< threadContexts
.size(); i
++)
335 TheISA::startupCPU(threadContexts
[i
], i
);
336 // Moved from the constructor to here since it relies on the
337 // address map being resolved in the interconnect
339 * Load the kernel code into memory
341 auto mapper
= [this](Addr a
) {
342 return (a
& loadAddrMask
) + loadAddrOffset
;
344 if (params()->kernel
!= "") {
345 if (params()->kernel_addr_check
) {
346 // Validate kernel mapping before loading binary
347 if (!isMemAddr(mapper(kernelStart
)) ||
348 !isMemAddr(mapper(kernelEnd
))) {
349 fatal("Kernel is mapped to invalid location (not memory). "
350 "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
351 kernelStart
, kernelEnd
,
352 mapper(kernelStart
), mapper(kernelEnd
));
355 // Load program sections into memory
356 kernelImage
.write(physProxy
);
357 for (const auto &extra_kernel
: kernelExtras
)
358 extra_kernel
->buildImage().move(mapper
).write(physProxy
);
360 DPRINTF(Loader
, "Kernel start = %#x\n", kernelStart
);
361 DPRINTF(Loader
, "Kernel end = %#x\n", kernelEnd
);
362 DPRINTF(Loader
, "Kernel entry = %#x\n", kernelEntry
);
363 DPRINTF(Loader
, "Kernel loaded...\n");
369 System::replaceThreadContext(ThreadContext
*tc
, ContextID context_id
)
371 if (context_id
>= threadContexts
.size()) {
372 panic("replaceThreadContext: bad id, %d >= %d\n",
373 context_id
, threadContexts
.size());
376 for (auto *e
: liveEvents
) {
377 threadContexts
[context_id
]->remove(e
);
380 threadContexts
[context_id
] = tc
;
381 if (context_id
< remoteGDB
.size())
382 remoteGDB
[context_id
]->replaceThreadContext(tc
);
386 System::validKvmEnvironment() const
389 if (threadContexts
.empty())
392 for (auto tc
: threadContexts
) {
393 if (dynamic_cast<BaseKvmCPU
*>(tc
->getCpuPtr()) == nullptr) {
404 System::allocPhysPages(int npages
)
406 Addr return_addr
= pagePtr
<< PageShift
;
409 Addr next_return_addr
= pagePtr
<< PageShift
;
411 AddrRange
m5opRange(0xffff0000, 0x100000000);
412 if (m5opRange
.contains(next_return_addr
)) {
413 warn("Reached m5ops MMIO region\n");
414 return_addr
= 0xffffffff;
415 pagePtr
= 0xffffffff >> PageShift
;
418 if ((pagePtr
<< PageShift
) > physmem
.totalSize())
419 fatal("Out of memory, please increase size of physical memory.");
424 System::memSize() const
426 return physmem
.totalSize();
430 System::freeMemSize() const
432 return physmem
.totalSize() - (pagePtr
<< PageShift
);
436 System::isMemAddr(Addr addr
) const
438 return physmem
.isMemAddr(addr
);
442 System::drainResume()
448 System::serialize(CheckpointOut
&cp
) const
451 kernelSymtab
->serialize("kernel_symtab", cp
);
452 SERIALIZE_SCALAR(pagePtr
);
455 // also serialize the memories in the system
456 physmem
.serializeSection(cp
, "physmem");
461 System::unserialize(CheckpointIn
&cp
)
464 kernelSymtab
->unserialize("kernel_symtab", cp
);
465 UNSERIALIZE_SCALAR(pagePtr
);
466 unserializeSymtab(cp
);
468 // also unserialize the memories in the system
469 physmem
.unserializeSection(cp
, "physmem");
475 SimObject::regStats();
477 for (uint32_t j
= 0; j
< numWorkIds
; j
++) {
478 workItemStats
[j
] = new Stats::Histogram();
479 stringstream namestr
;
480 ccprintf(namestr
, "work_item_type%d", j
);
481 workItemStats
[j
]->init(20)
482 .name(name() + "." + namestr
.str())
483 .desc("Run time stat for" + namestr
.str())
484 .prereq(*workItemStats
[j
]);
489 System::workItemEnd(uint32_t tid
, uint32_t workid
)
491 std::pair
<uint32_t,uint32_t> p(tid
, workid
);
492 if (!lastWorkItemStarted
.count(p
))
495 Tick samp
= curTick() - lastWorkItemStarted
[p
];
496 DPRINTF(WorkItems
, "Work item end: %d\t%d\t%lld\n", tid
, workid
, samp
);
498 if (workid
>= numWorkIds
)
499 fatal("Got workid greater than specified in system configuration\n");
501 workItemStats
[workid
]->sample(samp
);
502 lastWorkItemStarted
.erase(p
);
506 System::printSystems()
508 ios::fmtflags
flags(cerr
.flags());
510 vector
<System
*>::iterator i
= systemList
.begin();
511 vector
<System
*>::iterator end
= systemList
.end();
512 for (; i
!= end
; ++i
) {
514 cerr
<< "System " << sys
->name() << ": " << hex
<< sys
<< endl
;
523 System::printSystems();
527 System::stripSystemName(const std::string
& master_name
) const
529 if (startswith(master_name
, name())) {
530 return master_name
.substr(name().size());
537 System::lookupMasterId(const SimObject
* obj
) const
539 MasterID id
= Request::invldMasterId
;
541 // number of occurrences of the SimObject pointer
542 // in the master list.
545 for (int i
= 0; i
< masters
.size(); i
++) {
546 if (masters
[i
].obj
== obj
) {
552 fatal_if(obj_number
> 1,
553 "Cannot lookup MasterID by SimObject pointer: "
554 "More than one master is sharing the same SimObject\n");
560 System::lookupMasterId(const std::string
& master_name
) const
562 std::string name
= stripSystemName(master_name
);
564 for (int i
= 0; i
< masters
.size(); i
++) {
565 if (masters
[i
].masterName
== name
) {
570 return Request::invldMasterId
;
574 System::getGlobalMasterId(const std::string
& master_name
)
576 return _getMasterId(nullptr, master_name
);
580 System::getMasterId(const SimObject
* master
, std::string submaster
)
582 auto master_name
= leafMasterName(master
, submaster
);
583 return _getMasterId(master
, master_name
);
587 System::_getMasterId(const SimObject
* master
, const std::string
& master_name
)
589 std::string name
= stripSystemName(master_name
);
591 // CPUs in switch_cpus ask for ids again after switching
592 for (int i
= 0; i
< masters
.size(); i
++) {
593 if (masters
[i
].masterName
== name
) {
598 // Verify that the statistics haven't been enabled yet
599 // Otherwise objects will have sized their stat buckets and
600 // they will be too small
602 if (Stats::enabled()) {
603 fatal("Can't request a masterId after regStats(). "
604 "You must do so in init().\n");
607 // Generate a new MasterID incrementally
608 MasterID master_id
= masters
.size();
610 // Append the new Master metadata to the group of system Masters.
611 masters
.emplace_back(master
, name
, master_id
);
613 return masters
.back().masterId
;
617 System::leafMasterName(const SimObject
* master
, const std::string
& submaster
)
619 if (submaster
.empty()) {
620 return master
->name();
622 // Get the full master name by appending the submaster name to
623 // the root SimObject master name
624 return master
->name() + "." + submaster
;
629 System::getMasterName(MasterID master_id
)
631 if (master_id
>= masters
.size())
632 fatal("Invalid master_id passed to getMasterName()\n");
634 const auto& master_info
= masters
[master_id
];
635 return master_info
.masterName
;
639 SystemParams::create()
641 return new System(this);