2 * Copyright (c) 2011-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
48 #include "arch/isa_traits.hh"
49 #include "arch/remote_gdb.hh"
50 #include "arch/utility.hh"
51 #include "arch/vtophys.hh"
52 #include "base/loader/object_file.hh"
53 #include "base/loader/symtab.hh"
54 #include "base/str.hh"
55 #include "base/trace.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/Loader.hh"
59 #include "debug/WorkItems.hh"
60 #include "kern/kernel_stats.hh"
61 #include "mem/abstract_mem.hh"
62 #include "mem/physical.hh"
63 #include "params/System.hh"
64 #include "sim/byteswap.hh"
65 #include "sim/debug.hh"
66 #include "sim/full_system.hh"
67 #include "sim/system.hh"
70 using namespace TheISA
;
72 vector
<System
*> System::systemList
;
74 int System::numSystemsRunning
= 0;
76 System::System(Params
*p
)
77 : MemObject(p
), _systemPort("system_port", this),
80 init_param(p
->init_param
),
81 physProxy(_systemPort
, p
->cache_line_size
),
82 virtProxy(_systemPort
, p
->cache_line_size
),
83 loadAddrMask(p
->load_addr_mask
),
85 physmem(name() + ".physmem", p
->memories
),
86 memoryMode(p
->mem_mode
),
87 _cacheLineSize(p
->cache_line_size
),
90 numWorkIds(p
->num_work_ids
),
93 instEventQueue("system instruction-based event queue")
95 // add self to global system list
96 systemList
.push_back(this);
99 kernelSymtab
= new SymbolTable
;
100 if (!debugSymbolTable
)
101 debugSymbolTable
= new SymbolTable
;
104 // check if the cache line size is a value known to work
105 if (!(_cacheLineSize
== 16 || _cacheLineSize
== 32 ||
106 _cacheLineSize
== 64 || _cacheLineSize
== 128))
107 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
109 // Get the generic system master IDs
110 MasterID tmp_id M5_VAR_USED
;
111 tmp_id
= getMasterId("writebacks");
112 assert(tmp_id
== Request::wbMasterId
);
113 tmp_id
= getMasterId("functional");
114 assert(tmp_id
== Request::funcMasterId
);
115 tmp_id
= getMasterId("interrupt");
116 assert(tmp_id
== Request::intMasterId
);
119 if (params()->kernel
== "") {
120 inform("No kernel set for full system simulation. "
121 "Assuming you know what you're doing\n");
125 // Get the kernel code
126 kernel
= createObjectFile(params()->kernel
);
127 inform("kernel located at: %s", params()->kernel
);
130 fatal("Could not load kernel file %s", params()->kernel
);
132 // setup entry points
133 kernelStart
= kernel
->textBase();
134 kernelEnd
= kernel
->bssBase() + kernel
->bssSize();
135 kernelEntry
= kernel
->entryPoint();
138 if (!kernel
->loadGlobalSymbols(kernelSymtab
))
139 fatal("could not load kernel symbols\n");
141 if (!kernel
->loadLocalSymbols(kernelSymtab
))
142 fatal("could not load kernel local symbols\n");
144 if (!kernel
->loadGlobalSymbols(debugSymbolTable
))
145 fatal("could not load kernel symbols\n");
147 if (!kernel
->loadLocalSymbols(debugSymbolTable
))
148 fatal("could not load kernel local symbols\n");
150 // Loading only needs to happen once and after memory system is
151 // connected so it will happen in initState()
155 // increment the number of running systms
158 // Set back pointers to the system in all memories
159 for (int x
= 0; x
< params()->memories
.size(); x
++)
160 params()->memories
[x
]->system(this);
168 for (uint32_t j
= 0; j
< numWorkIds
; j
++)
169 delete workItemStats
[j
];
175 // check that the system port is connected
176 if (!_systemPort
.isConnected())
177 panic("System port on %s is not connected.\n", name());
181 System::getMasterPort(const std::string
&if_name
, PortID idx
)
183 // no need to distinguish at the moment (besides checking)
188 System::setMemoryMode(Enums::MemoryMode mode
)
190 assert(getDrainState() == Drainable::Drained
);
194 bool System::breakpoint()
196 if (remoteGDB
.size())
197 return remoteGDB
[0]->breakpoint();
202 * Setting rgdb_wait to a positive integer waits for a remote debugger to
203 * connect to that context ID before continuing. This should really
204 be a parameter on the CPU object or something...
209 System::registerThreadContext(ThreadContext
*tc
, int assigned
)
212 if (assigned
== -1) {
213 for (id
= 0; id
< threadContexts
.size(); id
++) {
214 if (!threadContexts
[id
])
218 if (threadContexts
.size() <= id
)
219 threadContexts
.resize(id
+ 1);
221 if (threadContexts
.size() <= assigned
)
222 threadContexts
.resize(assigned
+ 1);
226 if (threadContexts
[id
])
227 fatal("Cannot have two CPUs with the same id (%d)\n", id
);
229 threadContexts
[id
] = tc
;
232 int port
= getRemoteGDBPort();
234 RemoteGDB
*rgdb
= new RemoteGDB(this, tc
);
235 GDBListener
*gdbl
= new GDBListener(rgdb
, port
+ id
);
238 if (rgdb_wait
!= -1 && rgdb_wait
== id
)
241 if (remoteGDB
.size() <= id
) {
242 remoteGDB
.resize(id
+ 1);
245 remoteGDB
[id
] = rgdb
;
248 activeCpus
.push_back(false);
254 System::numRunningContexts()
257 for (int i
= 0; i
< _numContexts
; ++i
) {
258 if (threadContexts
[i
]->status() != ThreadContext::Halted
)
268 for (int i
= 0; i
< threadContexts
.size(); i
++)
269 TheISA::startupCPU(threadContexts
[i
], i
);
270 // Moved from the constructor to here since it relies on the
271 // address map being resolved in the interconnect
273 * Load the kernel code into memory
275 if (params()->kernel
!= "") {
276 // Validate kernel mapping before loading binary
277 if (!(isMemAddr(kernelStart
& loadAddrMask
) &&
278 isMemAddr(kernelEnd
& loadAddrMask
))) {
279 fatal("Kernel is mapped to invalid location (not memory). "
280 "kernelStart 0x(%x) - kernelEnd 0x(%x)\n", kernelStart
,
283 // Load program sections into memory
284 kernel
->loadSections(physProxy
, loadAddrMask
);
286 DPRINTF(Loader
, "Kernel start = %#x\n", kernelStart
);
287 DPRINTF(Loader
, "Kernel end = %#x\n", kernelEnd
);
288 DPRINTF(Loader
, "Kernel entry = %#x\n", kernelEntry
);
289 DPRINTF(Loader
, "Kernel loaded...\n");
297 System::replaceThreadContext(ThreadContext
*tc
, int context_id
)
299 if (context_id
>= threadContexts
.size()) {
300 panic("replaceThreadContext: bad id, %d >= %d\n",
301 context_id
, threadContexts
.size());
304 threadContexts
[context_id
] = tc
;
305 if (context_id
< remoteGDB
.size())
306 remoteGDB
[context_id
]->replaceThreadContext(tc
);
310 System::allocPhysPages(int npages
)
312 Addr return_addr
= pagePtr
<< LogVMPageSize
;
314 if ((pagePtr
<< LogVMPageSize
) > physmem
.totalSize())
315 fatal("Out of memory, please increase size of physical memory.");
320 System::memSize() const
322 return physmem
.totalSize();
326 System::freeMemSize() const
328 return physmem
.totalSize() - (pagePtr
<< LogVMPageSize
);
332 System::isMemAddr(Addr addr
) const
334 return physmem
.isMemAddr(addr
);
338 System::drain(DrainManager
*dm
)
340 setDrainState(Drainable::Drained
);
345 System::drainResume()
347 Drainable::drainResume();
352 System::serialize(ostream
&os
)
355 kernelSymtab
->serialize("kernel_symtab", os
);
356 SERIALIZE_SCALAR(pagePtr
);
357 SERIALIZE_SCALAR(nextPID
);
360 // also serialize the memories in the system
361 nameOut(os
, csprintf("%s.physmem", name()));
362 physmem
.serialize(os
);
367 System::unserialize(Checkpoint
*cp
, const string
§ion
)
370 kernelSymtab
->unserialize("kernel_symtab", cp
, section
);
371 UNSERIALIZE_SCALAR(pagePtr
);
372 UNSERIALIZE_SCALAR(nextPID
);
373 unserializeSymtab(cp
, section
);
375 // also unserialize the memories in the system
376 physmem
.unserialize(cp
, csprintf("%s.physmem", name()));
382 for (uint32_t j
= 0; j
< numWorkIds
; j
++) {
383 workItemStats
[j
] = new Stats::Histogram();
384 stringstream namestr
;
385 ccprintf(namestr
, "work_item_type%d", j
);
386 workItemStats
[j
]->init(20)
387 .name(name() + "." + namestr
.str())
388 .desc("Run time stat for" + namestr
.str())
389 .prereq(*workItemStats
[j
]);
394 System::workItemEnd(uint32_t tid
, uint32_t workid
)
396 std::pair
<uint32_t,uint32_t> p(tid
, workid
);
397 if (!lastWorkItemStarted
.count(p
))
400 Tick samp
= curTick() - lastWorkItemStarted
[p
];
401 DPRINTF(WorkItems
, "Work item end: %d\t%d\t%lld\n", tid
, workid
, samp
);
403 if (workid
>= numWorkIds
)
404 fatal("Got workid greater than specified in system configuration\n");
406 workItemStats
[workid
]->sample(samp
);
407 lastWorkItemStarted
.erase(p
);
411 System::printSystems()
413 vector
<System
*>::iterator i
= systemList
.begin();
414 vector
<System
*>::iterator end
= systemList
.end();
415 for (; i
!= end
; ++i
) {
417 cerr
<< "System " << sys
->name() << ": " << hex
<< sys
<< endl
;
424 System::printSystems();
428 System::getMasterId(std::string master_name
)
430 // strip off system name if the string starts with it
431 if (startswith(master_name
, name()))
432 master_name
= master_name
.erase(0, name().size() + 1);
434 // CPUs in switch_cpus ask for ids again after switching
435 for (int i
= 0; i
< masterIds
.size(); i
++) {
436 if (masterIds
[i
] == master_name
) {
441 // Verify that the statistics haven't been enabled yet
442 // Otherwise objects will have sized their stat buckets and
443 // they will be too small
445 if (Stats::enabled())
446 fatal("Can't request a masterId after regStats(). \
447 You must do so in init().\n");
449 masterIds
.push_back(master_name
);
451 return masterIds
.size() - 1;
455 System::getMasterName(MasterID master_id
)
457 if (master_id
>= masterIds
.size())
458 fatal("Invalid master_id passed to getMasterName()\n");
460 return masterIds
[master_id
];
463 const char *System::MemoryModeStrings
[4] = {"invalid", "atomic", "timing",
464 "atomic_noncaching"};
467 SystemParams::create()
469 return new System(this);