2 * Copyright (c) 2012, 2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
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19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
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24 * documentation and/or other materials provided with the distribution;
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27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
51 #include <unordered_map>
55 #include "arch/isa_traits.hh"
56 #include "base/loader/symtab.hh"
57 #include "base/statistics.hh"
58 #include "config/the_isa.hh"
59 #include "enums/MemoryMode.hh"
60 #include "mem/mem_object.hh"
61 #include "mem/physical.hh"
62 #include "mem/port.hh"
63 #include "mem/port_proxy.hh"
64 #include "params/System.hh"
65 #include "sim/futex_map.hh"
66 #include "sim/se_signal.hh"
69 * To avoid linking errors with LTO, only include the header if we
70 * actually have the definition.
72 #if THE_ISA != NULL_ISA
73 #include "cpu/pc_event.hh"
83 class System : public MemObject
88 * Private class for the system port which is only used as a
89 * master for debug access and for non-structural entities that do
90 * not have a port of their own.
92 class SystemPort : public MasterPort
97 * Create a system port with a name and an owner.
99 SystemPort(const std::string &_name, MemObject *_owner)
100 : MasterPort(_name, _owner)
102 bool recvTimingResp(PacketPtr pkt) override
103 { panic("SystemPort does not receive timing!\n"); return false; }
104 void recvReqRetry() override
105 { panic("SystemPort does not expect retry!\n"); }
108 SystemPort _systemPort;
113 * After all objects have been created and all ports are
114 * connected, check that the system port is connected.
116 void init() override;
119 * Get a reference to the system port that can be used by
120 * non-structural simulation objects like processes or threads, or
121 * external entities like loaders and debuggers, etc, to access
124 * @return a reference to the system port we own
126 MasterPort& getSystemPort() { return _systemPort; }
129 * Additional function to return the Port of a memory object.
131 BaseMasterPort& getMasterPort(const std::string &if_name,
132 PortID idx = InvalidPortID) override;
136 * Is the system in atomic mode?
138 * There are currently two different atomic memory modes:
139 * 'atomic', which supports caches; and 'atomic_noncaching', which
140 * bypasses caches. The latter is used by hardware virtualized
141 * CPUs. SimObjects are expected to use Port::sendAtomic() and
142 * Port::recvAtomic() when accessing memory in this mode.
144 bool isAtomicMode() const {
145 return memoryMode == Enums::atomic ||
146 memoryMode == Enums::atomic_noncaching;
150 * Is the system in timing mode?
152 * SimObjects are expected to use Port::sendTiming() and
153 * Port::recvTiming() when accessing memory in this mode.
155 bool isTimingMode() const {
156 return memoryMode == Enums::timing;
160 * Should caches be bypassed?
162 * Some CPUs need to bypass caches to allow direct memory
163 * accesses, which is required for hardware virtualization.
165 bool bypassCaches() const {
166 return memoryMode == Enums::atomic_noncaching;
172 * Get the memory mode of the system.
174 * \warn This should only be used by the Python world. The C++
175 * world should use one of the query functions above
176 * (isAtomicMode(), isTimingMode(), bypassCaches()).
178 Enums::MemoryMode getMemoryMode() const { return memoryMode; }
181 * Change the memory mode of the system.
183 * \warn This should only be called by the Python!
185 * @param mode Mode to change to (atomic/timing/...)
187 void setMemoryMode(Enums::MemoryMode mode);
191 * Get the cache line size of the system.
193 unsigned int cacheLineSize() const { return _cacheLineSize; }
195 #if THE_ISA != NULL_ISA
196 PCEventQueue pcEventQueue;
199 std::vector<ThreadContext *> threadContexts;
201 const bool multiThread;
203 ThreadContext *getThreadContext(ContextID tid)
205 return threadContexts[tid];
210 assert(_numContexts == (int)threadContexts.size());
214 /** Return number of running (non-halted) thread contexts in
215 * system. These threads could be Active or Suspended. */
216 int numRunningContexts();
222 /** Port to physical memory used for writing object files into ram at
226 /** kernel symbol table */
227 SymbolTable *kernelSymtab;
229 /** Object pointer for the kernel code */
232 /** Beginning of kernel code */
235 /** End of kernel code */
238 /** Entry point in the kernel to start at */
241 /** Mask that should be anded for binary/symbol loading.
242 * This allows one two different OS requirements for the same ISA to be
243 * handled. Some OSes are compiled for a virtual address and need to be
244 * loaded into physical memory that starts at address 0, while other
245 * bare metal tools generate images that start at address 0.
249 /** Offset that should be used for binary/symbol loading.
250 * This further allows more flexibility than the loadAddrMask allows alone
251 * in loading kernels and similar. The loadAddrOffset is applied after the
258 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject,
265 /** Verify gem5 configuration will support KVM emulation */
266 bool validKvmEnvironment() const;
268 /** Get a pointer to access the physical memory of the system */
269 PhysicalMemory& getPhysMem() { return physmem; }
271 /** Amount of physical memory that is still free */
272 Addr freeMemSize() const;
274 /** Amount of physical memory that exists */
275 Addr memSize() const;
278 * Check if a physical address is within a range of a memory that
279 * is part of the global address map.
281 * @param addr A physical address
282 * @return Whether the address corresponds to a memory
284 bool isMemAddr(Addr addr) const;
287 * Get the architecture.
289 Arch getArch() const { return Arch::TheISA; }
292 * Get the page bytes for the ISA.
294 Addr getPageBytes() const { return TheISA::PageBytes; }
297 * Get the number of bits worth of in-page address for the ISA.
299 Addr getPageShift() const { return TheISA::PageShift; }
302 * The thermal model used for this system (if any).
304 ThermalModel * getThermalModel() const { return thermalModel; }
310 PhysicalMemory physmem;
312 Enums::MemoryMode memoryMode;
314 const unsigned int _cacheLineSize;
316 uint64_t workItemsBegin;
317 uint64_t workItemsEnd;
319 std::vector<bool> activeCpus;
321 /** This array is a per-system list of all devices capable of issuing a
322 * memory system request and an associated string for each master id.
323 * It's used to uniquely id any master in the system by name for things
324 * like cache statistics.
326 std::vector<std::string> masterIds;
328 ThermalModel * thermalModel;
332 /** Request an id used to create a request object in the system. All objects
333 * that intend to issues requests into the memory system must request an id
334 * in the init() phase of startup. All master ids must be fixed by the
335 * regStats() phase that immediately precedes it. This allows objects in
336 * the memory system to understand how many masters may exist and
337 * appropriately name the bins of their per-master stats before the stats
340 MasterID getMasterId(std::string req_name);
342 /** Get the name of an object for a given request id.
344 std::string getMasterName(MasterID master_id);
346 /** Get the number of masters registered in the system */
347 MasterID maxMasters()
349 return masterIds.size();
352 void regStats() override;
354 * Called by pseudo_inst to track the number of work items started by this
360 return ++workItemsBegin;
364 * Called by pseudo_inst to track the number of work items completed by
370 return ++workItemsEnd;
374 * Called by pseudo_inst to mark the cpus actively executing work items.
375 * Returns the total number of cpus that have executed work item begin or
379 markWorkItem(int index)
382 assert(index < activeCpus.size());
383 activeCpus[index] = true;
384 for (std::vector<bool>::iterator i = activeCpus.begin();
385 i < activeCpus.end(); i++) {
391 inline void workItemBegin(uint32_t tid, uint32_t workid)
393 std::pair<uint32_t,uint32_t> p(tid, workid);
394 lastWorkItemStarted[p] = curTick();
397 void workItemEnd(uint32_t tid, uint32_t workid);
400 * Fix up an address used to match PCs for hooking simulator
401 * events on to target function executions. See comment in
402 * system.cc for details.
404 virtual Addr fixFuncEventAddr(Addr addr)
406 panic("Base fixFuncEventAddr not implemented.\n");
411 * Add a function-based event to the given function, to be looked
412 * up in the specified symbol table.
414 * The ...OrPanic flavor of the method causes the simulator to
415 * panic if the symbol can't be found.
417 * @param symtab Symbol table to use for look up.
418 * @param lbl Function to hook the event to.
419 * @param desc Description to be passed to the event.
420 * @param args Arguments to be forwarded to the event constructor.
422 template <class T, typename... Args>
423 T *addFuncEvent(const SymbolTable *symtab, const char *lbl,
424 const std::string &desc, Args... args)
426 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
428 #if THE_ISA != NULL_ISA
429 if (symtab->findAddress(lbl, addr)) {
430 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
431 std::forward<Args>(args)...);
440 T *addFuncEvent(const SymbolTable *symtab, const char *lbl)
442 return addFuncEvent<T>(symtab, lbl, lbl);
445 template <class T, typename... Args>
446 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl,
449 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...));
451 panic("Failed to find symbol '%s'", lbl);
458 * Add a function-based event to a kernel symbol.
460 * These functions work like their addFuncEvent() and
461 * addFuncEventOrPanic() counterparts. The only difference is that
462 * they automatically use the kernel symbol table. All arguments
463 * are forwarded to the underlying method.
465 * @see addFuncEvent()
466 * @see addFuncEventOrPanic()
468 * @param lbl Function to hook the event to.
469 * @param args Arguments to be passed to addFuncEvent
471 template <class T, typename... Args>
472 T *addKernelFuncEvent(const char *lbl, Args... args)
474 return addFuncEvent<T>(kernelSymtab, lbl,
475 std::forward<Args>(args)...);
478 template <class T, typename... Args>
479 T *addKernelFuncEventOrPanic(const char *lbl, Args... args)
481 T *e(addFuncEvent<T>(kernelSymtab, lbl,
482 std::forward<Args>(args)...));
484 panic("Failed to find kernel symbol '%s'", lbl);
490 std::vector<BaseRemoteGDB *> remoteGDB;
491 std::vector<GDBListener *> gdbListen;
495 typedef SystemParams Params;
504 void initState() override;
506 const Params *params() const { return (const Params *)_params; }
511 * Returns the address the kernel starts at.
512 * @return address the kernel starts at
514 Addr getKernelStart() const { return kernelStart; }
517 * Returns the address the kernel ends at.
518 * @return address the kernel ends at
520 Addr getKernelEnd() const { return kernelEnd; }
523 * Returns the address the entry point to the kernel code.
524 * @return entry point of the kernel code
526 Addr getKernelEntry() const { return kernelEntry; }
528 /// Allocate npages contiguous unused physical pages
529 /// @return Starting address of first page
530 Addr allocPhysPages(int npages);
532 ContextID registerThreadContext(ThreadContext *tc,
533 ContextID assigned = InvalidContextID);
534 void replaceThreadContext(ThreadContext *tc, ContextID context_id);
536 void serialize(CheckpointOut &cp) const override;
537 void unserialize(CheckpointIn &cp) override;
539 void drainResume() override;
542 Counter totalNumInsts;
543 EventQueue instEventQueue;
544 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
545 std::map<uint32_t, Stats::Histogram*> workItemStats;
547 ////////////////////////////////////////////
549 // STATIC GLOBAL SYSTEM LIST
551 ////////////////////////////////////////////
553 static std::vector<System *> systemList;
554 static int numSystemsRunning;
556 static void printSystems();
560 static const int maxPID = 32768;
562 /** Process set to track which PIDs have already been allocated */
565 // By convention, all signals are owned by the receiving process. The
566 // receiver will delete the signal upon reception.
567 std::list<BasicSignal> signalList;
572 * If needed, serialize additional symbol table entries for a
573 * specific subclass of this system. Currently this is used by
576 * @param os stream to serialize to
578 virtual void serializeSymtab(CheckpointOut &os) const {}
581 * If needed, unserialize additional symbol table entries for a
582 * specific subclass of this system.
584 * @param cp checkpoint to unserialize from
585 * @param section relevant section in the checkpoint
587 virtual void unserializeSymtab(CheckpointIn &cp) {}
593 #endif // __SYSTEM_HH__