src/sim/system.hh

   1 /*
   2  * Copyright (c) 2012, 2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Lisa Hsu
  43  *          Nathan Binkert
  44  *          Rick Strong
  45  */
  46
  47 #ifndef __SYSTEM_HH__
  48 #define __SYSTEM_HH__
  49
  50 #include <string>
  51 #include <unordered_map>
  52 #include <utility>
  53 #include <vector>
  54
  55 #include "arch/isa_traits.hh"
  56 #include "base/loader/symtab.hh"
  57 #include "base/statistics.hh"
  58 #include "config/the_isa.hh"
  59 #include "enums/MemoryMode.hh"
  60 #include "mem/mem_object.hh"
  61 #include "mem/physical.hh"
  62 #include "mem/port.hh"
  63 #include "mem/port_proxy.hh"
  64 #include "params/System.hh"
  65 #include "sim/futex_map.hh"
  66 #include "sim/se_signal.hh"
  67
  68 /**
  69  * To avoid linking errors with LTO, only include the header if we
  70  * actually have the definition.
  71  */
  72 #if THE_ISA != NULL_ISA
  73 #include "cpu/pc_event.hh"
  74
  75 #endif
  76
  77 class BaseRemoteGDB;
  78 class GDBListener;
  79 class KvmVM;
  80 class ObjectFile;
  81 class ThreadContext;
  82
  83 class System : public MemObject
  84 {
  85   private:
  86
  87     /**
  88      * Private class for the system port which is only used as a
  89      * master for debug access and for non-structural entities that do
  90      * not have a port of their own.
  91      */
  92     class SystemPort : public MasterPort
  93     {
  94       public:
  95
  96         /**
  97          * Create a system port with a name and an owner.
  98          */
  99         SystemPort(const std::string &_name, MemObject *_owner)
 100             : MasterPort(_name, _owner)
 101         { }
 102         bool recvTimingResp(PacketPtr pkt) override
 103         { panic("SystemPort does not receive timing!\n"); return false; }
 104         void recvReqRetry() override
 105         { panic("SystemPort does not expect retry!\n"); }
 106     };
 107
 108     SystemPort _systemPort;
 109
 110   public:
 111
 112     /**
 113      * After all objects have been created and all ports are
 114      * connected, check that the system port is connected.
 115      */
 116     void init() override;
 117
 118     /**
 119      * Get a reference to the system port that can be used by
 120      * non-structural simulation objects like processes or threads, or
 121      * external entities like loaders and debuggers, etc, to access
 122      * the memory system.
 123      *
 124      * @return a reference to the system port we own
 125      */
 126     MasterPort& getSystemPort() { return _systemPort; }
 127
 128     /**
 129      * Additional function to return the Port of a memory object.
 130      */
 131     BaseMasterPort& getMasterPort(const std::string &if_name,
 132                                   PortID idx = InvalidPortID) override;
 133
 134     /** @{ */
 135     /**
 136      * Is the system in atomic mode?
 137      *
 138      * There are currently two different atomic memory modes:
 139      * 'atomic', which supports caches; and 'atomic_noncaching', which
 140      * bypasses caches. The latter is used by hardware virtualized
 141      * CPUs. SimObjects are expected to use Port::sendAtomic() and
 142      * Port::recvAtomic() when accessing memory in this mode.
 143      */
 144     bool isAtomicMode() const {
 145         return memoryMode == Enums::atomic ||
 146             memoryMode == Enums::atomic_noncaching;
 147     }
 148
 149     /**
 150      * Is the system in timing mode?
 151      *
 152      * SimObjects are expected to use Port::sendTiming() and
 153      * Port::recvTiming() when accessing memory in this mode.
 154      */
 155     bool isTimingMode() const {
 156         return memoryMode == Enums::timing;
 157     }
 158
 159     /**
 160      * Should caches be bypassed?
 161      *
 162      * Some CPUs need to bypass caches to allow direct memory
 163      * accesses, which is required for hardware virtualization.
 164      */
 165     bool bypassCaches() const {
 166         return memoryMode == Enums::atomic_noncaching;
 167     }
 168     /** @} */
 169
 170     /** @{ */
 171     /**
 172      * Get the memory mode of the system.
 173      *
 174      * \warn This should only be used by the Python world. The C++
 175      * world should use one of the query functions above
 176      * (isAtomicMode(), isTimingMode(), bypassCaches()).
 177      */
 178     Enums::MemoryMode getMemoryMode() const { return memoryMode; }
 179
 180     /**
 181      * Change the memory mode of the system.
 182      *
 183      * \warn This should only be called by the Python!
 184      *
 185      * @param mode Mode to change to (atomic/timing/...)
 186      */
 187     void setMemoryMode(Enums::MemoryMode mode);
 188     /** @} */
 189
 190     /**
 191      * Get the cache line size of the system.
 192      */
 193     unsigned int cacheLineSize() const { return _cacheLineSize; }
 194
 195 #if THE_ISA != NULL_ISA
 196     PCEventQueue pcEventQueue;
 197 #endif
 198
 199     std::vector<ThreadContext *> threadContexts;
 200     int _numContexts;
 201     const bool multiThread;
 202
 203     ThreadContext *getThreadContext(ContextID tid)
 204     {
 205         return threadContexts[tid];
 206     }
 207
 208     int numContexts()
 209     {
 210         assert(_numContexts == (int)threadContexts.size());
 211         return _numContexts;
 212     }
 213
 214     /** Return number of running (non-halted) thread contexts in
 215      * system.  These threads could be Active or Suspended. */
 216     int numRunningContexts();
 217
 218     Addr pagePtr;
 219
 220     uint64_t init_param;
 221
 222     /** Port to physical memory used for writing object files into ram at
 223      * boot.*/
 224     PortProxy physProxy;
 225
 226     /** kernel symbol table */
 227     SymbolTable *kernelSymtab;
 228
 229     /** Object pointer for the kernel code */
 230     ObjectFile *kernel;
 231
 232     /** Beginning of kernel code */
 233     Addr kernelStart;
 234
 235     /** End of kernel code */
 236     Addr kernelEnd;
 237
 238     /** Entry point in the kernel to start at */
 239     Addr kernelEntry;
 240
 241     /** Mask that should be anded for binary/symbol loading.
 242      * This allows one two different OS requirements for the same ISA to be
 243      * handled.  Some OSes are compiled for a virtual address and need to be
 244      * loaded into physical memory that starts at address 0, while other
 245      * bare metal tools generate images that start at address 0.
 246      */
 247     Addr loadAddrMask;
 248
 249     /** Offset that should be used for binary/symbol loading.
 250      * This further allows more flexibility than the loadAddrMask allows alone
 251      * in loading kernels and similar. The loadAddrOffset is applied after the
 252      * loadAddrMask.
 253      */
 254     Addr loadAddrOffset;
 255
 256   public:
 257     /**
 258      * Get a pointer to the Kernel Virtual Machine (KVM) SimObject,
 259      * if present.
 260      */
 261     KvmVM* getKvmVM() {
 262         return kvmVM;
 263     }
 264
 265     /** Get a pointer to access the physical memory of the system */
 266     PhysicalMemory& getPhysMem() { return physmem; }
 267
 268     /** Amount of physical memory that is still free */
 269     Addr freeMemSize() const;
 270
 271     /** Amount of physical memory that exists */
 272     Addr memSize() const;
 273
 274     /**
 275      * Check if a physical address is within a range of a memory that
 276      * is part of the global address map.
 277      *
 278      * @param addr A physical address
 279      * @return Whether the address corresponds to a memory
 280      */
 281     bool isMemAddr(Addr addr) const;
 282
 283     /**
 284      * Get the architecture.
 285      */
 286     Arch getArch() const { return Arch::TheISA; }
 287
 288      /**
 289      * Get the page bytes for the ISA.
 290      */
 291     Addr getPageBytes() const { return TheISA::PageBytes; }
 292
 293     /**
 294      * Get the number of bits worth of in-page address for the ISA.
 295      */
 296     Addr getPageShift() const { return TheISA::PageShift; }
 297
 298     /**
 299      * The thermal model used for this system (if any).
 300      */
 301     ThermalModel * getThermalModel() const { return thermalModel; }
 302
 303   protected:
 304
 305     KvmVM *const kvmVM;
 306
 307     PhysicalMemory physmem;
 308
 309     Enums::MemoryMode memoryMode;
 310
 311     const unsigned int _cacheLineSize;
 312
 313     uint64_t workItemsBegin;
 314     uint64_t workItemsEnd;
 315     uint32_t numWorkIds;
 316     std::vector<bool> activeCpus;
 317
 318     /** This array is a per-system list of all devices capable of issuing a
 319      * memory system request and an associated string for each master id.
 320      * It's used to uniquely id any master in the system by name for things
 321      * like cache statistics.
 322      */
 323     std::vector<std::string> masterIds;
 324
 325     ThermalModel * thermalModel;
 326
 327   public:
 328
 329     /** Request an id used to create a request object in the system. All objects
 330      * that intend to issues requests into the memory system must request an id
 331      * in the init() phase of startup. All master ids must be fixed by the
 332      * regStats() phase that immediately precedes it. This allows objects in
 333      * the memory system to understand how many masters may exist and
 334      * appropriately name the bins of their per-master stats before the stats
 335      * are finalized
 336      */
 337     MasterID getMasterId(std::string req_name);
 338
 339     /** Get the name of an object for a given request id.
 340      */
 341     std::string getMasterName(MasterID master_id);
 342
 343     /** Get the number of masters registered in the system */
 344     MasterID maxMasters()
 345     {
 346         return masterIds.size();
 347     }
 348
 349     void regStats() override;
 350     /**
 351      * Called by pseudo_inst to track the number of work items started by this
 352      * system.
 353      */
 354     uint64_t
 355     incWorkItemsBegin()
 356     {
 357         return ++workItemsBegin;
 358     }
 359
 360     /**
 361      * Called by pseudo_inst to track the number of work items completed by
 362      * this system.
 363      */
 364     uint64_t
 365     incWorkItemsEnd()
 366     {
 367         return ++workItemsEnd;
 368     }
 369
 370     /**
 371      * Called by pseudo_inst to mark the cpus actively executing work items.
 372      * Returns the total number of cpus that have executed work item begin or
 373      * ends.
 374      */
 375     int
 376     markWorkItem(int index)
 377     {
 378         int count = 0;
 379         assert(index < activeCpus.size());
 380         activeCpus[index] = true;
 381         for (std::vector<bool>::iterator i = activeCpus.begin();
 382              i < activeCpus.end(); i++) {
 383             if (*i) count++;
 384         }
 385         return count;
 386     }
 387
 388     inline void workItemBegin(uint32_t tid, uint32_t workid)
 389     {
 390         std::pair<uint32_t,uint32_t> p(tid, workid);
 391         lastWorkItemStarted[p] = curTick();
 392     }
 393
 394     void workItemEnd(uint32_t tid, uint32_t workid);
 395
 396     /**
 397      * Fix up an address used to match PCs for hooking simulator
 398      * events on to target function executions.  See comment in
 399      * system.cc for details.
 400      */
 401     virtual Addr fixFuncEventAddr(Addr addr)
 402     {
 403         panic("Base fixFuncEventAddr not implemented.\n");
 404     }
 405
 406     /** @{ */
 407     /**
 408      * Add a function-based event to the given function, to be looked
 409      * up in the specified symbol table.
 410      *
 411      * The ...OrPanic flavor of the method causes the simulator to
 412      * panic if the symbol can't be found.
 413      *
 414      * @param symtab Symbol table to use for look up.
 415      * @param lbl Function to hook the event to.
 416      * @param desc Description to be passed to the event.
 417      * @param args Arguments to be forwarded to the event constructor.
 418      */
 419     template <class T, typename... Args>
 420     T *addFuncEvent(const SymbolTable *symtab, const char *lbl,
 421                     const std::string &desc, Args... args)
 422     {
 423         Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
 424
 425 #if THE_ISA != NULL_ISA
 426         if (symtab->findAddress(lbl, addr)) {
 427             T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
 428                           std::forward<Args>(args)...);
 429             return ev;
 430         }
 431 #endif
 432
 433         return NULL;
 434     }
 435
 436     template <class T>
 437     T *addFuncEvent(const SymbolTable *symtab, const char *lbl)
 438     {
 439         return addFuncEvent<T>(symtab, lbl, lbl);
 440     }
 441
 442     template <class T, typename... Args>
 443     T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl,
 444                            Args... args)
 445     {
 446         T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...));
 447         if (!e)
 448             panic("Failed to find symbol '%s'", lbl);
 449         return e;
 450     }
 451     /** @} */
 452
 453     /** @{ */
 454     /**
 455      * Add a function-based event to a kernel symbol.
 456      *
 457      * These functions work like their addFuncEvent() and
 458      * addFuncEventOrPanic() counterparts. The only difference is that
 459      * they automatically use the kernel symbol table. All arguments
 460      * are forwarded to the underlying method.
 461      *
 462      * @see addFuncEvent()
 463      * @see addFuncEventOrPanic()
 464      *
 465      * @param lbl Function to hook the event to.
 466      * @param args Arguments to be passed to addFuncEvent
 467      */
 468     template <class T, typename... Args>
 469     T *addKernelFuncEvent(const char *lbl, Args... args)
 470     {
 471         return addFuncEvent<T>(kernelSymtab, lbl,
 472                                std::forward<Args>(args)...);
 473     }
 474
 475     template <class T, typename... Args>
 476     T *addKernelFuncEventOrPanic(const char *lbl, Args... args)
 477     {
 478         T *e(addFuncEvent<T>(kernelSymtab, lbl,
 479                              std::forward<Args>(args)...));
 480         if (!e)
 481             panic("Failed to find kernel symbol '%s'", lbl);
 482         return e;
 483     }
 484     /** @} */
 485
 486   public:
 487     std::vector<BaseRemoteGDB *> remoteGDB;
 488     std::vector<GDBListener *> gdbListen;
 489     bool breakpoint();
 490
 491   public:
 492     typedef SystemParams Params;
 493
 494   protected:
 495     Params *_params;
 496
 497   public:
 498     System(Params *p);
 499     ~System();
 500
 501     void initState() override;
 502
 503     const Params *params() const { return (const Params *)_params; }
 504
 505   public:
 506
 507     /**
 508      * Returns the address the kernel starts at.
 509      * @return address the kernel starts at
 510      */
 511     Addr getKernelStart() const { return kernelStart; }
 512
 513     /**
 514      * Returns the address the kernel ends at.
 515      * @return address the kernel ends at
 516      */
 517     Addr getKernelEnd() const { return kernelEnd; }
 518
 519     /**
 520      * Returns the address the entry point to the kernel code.
 521      * @return entry point of the kernel code
 522      */
 523     Addr getKernelEntry() const { return kernelEntry; }
 524
 525     /// Allocate npages contiguous unused physical pages
 526     /// @return Starting address of first page
 527     Addr allocPhysPages(int npages);
 528
 529     ContextID registerThreadContext(ThreadContext *tc,
 530                                     ContextID assigned = InvalidContextID);
 531     void replaceThreadContext(ThreadContext *tc, ContextID context_id);
 532
 533     void serialize(CheckpointOut &cp) const override;
 534     void unserialize(CheckpointIn &cp) override;
 535
 536     void drainResume() override;
 537
 538   public:
 539     Counter totalNumInsts;
 540     EventQueue instEventQueue;
 541     std::map<std::pair<uint32_t,uint32_t>, Tick>  lastWorkItemStarted;
 542     std::map<uint32_t, Stats::Histogram*> workItemStats;
 543
 544     ////////////////////////////////////////////
 545     //
 546     // STATIC GLOBAL SYSTEM LIST
 547     //
 548     ////////////////////////////////////////////
 549
 550     static std::vector<System *> systemList;
 551     static int numSystemsRunning;
 552
 553     static void printSystems();
 554
 555     FutexMap futexMap;
 556
 557     static const int maxPID = 32768;
 558
 559     /** Process set to track which PIDs have already been allocated */
 560     std::set<int> PIDs;
 561
 562     // By convention, all signals are owned by the receiving process. The
 563     // receiver will delete the signal upon reception.
 564     std::list<BasicSignal> signalList;
 565
 566   protected:
 567
 568     /**
 569      * If needed, serialize additional symbol table entries for a
 570      * specific subclass of this system. Currently this is used by
 571      * Alpha and MIPS.
 572      *
 573      * @param os stream to serialize to
 574      */
 575     virtual void serializeSymtab(CheckpointOut &os) const {}
 576
 577     /**
 578      * If needed, unserialize additional symbol table entries for a
 579      * specific subclass of this system.
 580      *
 581      * @param cp checkpoint to unserialize from
 582      * @param section relevant section in the checkpoint
 583      */
 584     virtual void unserializeSymtab(CheckpointIn &cp) {}
 585
 586 };
 587
 588 void printSystems();
 589
 590 #endif // __SYSTEM_HH__