src/sim/system.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Lisa Hsu
  43  *          Nathan Binkert
  44  *          Rick Strong
  45  */
  46
  47 #ifndef __SYSTEM_HH__
  48 #define __SYSTEM_HH__
  49
  50 #include <string>
  51 #include <vector>
  52
  53 #include "base/loader/symtab.hh"
  54 #include "base/misc.hh"
  55 #include "base/statistics.hh"
  56 #include "cpu/pc_event.hh"
  57 #include "enums/MemoryMode.hh"
  58 #include "kern/system_events.hh"
  59 #include "mem/fs_translating_port_proxy.hh"
  60 #include "mem/mem_object.hh"
  61 #include "mem/port.hh"
  62 #include "mem/physical.hh"
  63 #include "params/System.hh"
  64
  65 class BaseCPU;
  66 class BaseRemoteGDB;
  67 class GDBListener;
  68 class ObjectFile;
  69 class Platform;
  70 class ThreadContext;
  71
  72 class System : public MemObject
  73 {
  74   private:
  75
  76     /**
  77      * Private class for the system port which is only used as a
  78      * master for debug access and for non-structural entities that do
  79      * not have a port of their own.
  80      */
  81     class SystemPort : public MasterPort
  82     {
  83       public:
  84
  85         /**
  86          * Create a system port with a name and an owner.
  87          */
  88         SystemPort(const std::string &_name, MemObject *_owner)
  89             : MasterPort(_name, _owner)
  90         { }
  91         bool recvTimingResp(PacketPtr pkt)
  92         { panic("SystemPort does not receive timing!\n"); return false; }
  93         void recvRetry()
  94         { panic("SystemPort does not expect retry!\n"); }
  95     };
  96
  97     SystemPort _systemPort;
  98
  99   public:
 100
 101     /**
 102      * After all objects have been created and all ports are
 103      * connected, check that the system port is connected.
 104      */
 105     virtual void init();
 106
 107     /**
 108      * Get a reference to the system port that can be used by
 109      * non-structural simulation objects like processes or threads, or
 110      * external entities like loaders and debuggers, etc, to access
 111      * the memory system.
 112      *
 113      * @return a reference to the system port we own
 114      */
 115     MasterPort& getSystemPort() { return _systemPort; }
 116
 117     /**
 118      * Additional function to return the Port of a memory object.
 119      */
 120     BaseMasterPort& getMasterPort(const std::string &if_name,
 121                                   PortID idx = InvalidPortID);
 122
 123     static const char *MemoryModeStrings[3];
 124
 125     Enums::MemoryMode
 126     getMemoryMode()
 127     {
 128         assert(memoryMode);
 129         return memoryMode;
 130     }
 131
 132     /** Change the memory mode of the system. This should only be called by the
 133      * python!!
 134      * @param mode Mode to change to (atomic/timing)
 135      */
 136     void setMemoryMode(Enums::MemoryMode mode);
 137
 138     PCEventQueue pcEventQueue;
 139
 140     std::vector<ThreadContext *> threadContexts;
 141     int _numContexts;
 142
 143     ThreadContext *getThreadContext(ThreadID tid)
 144     {
 145         return threadContexts[tid];
 146     }
 147
 148     int numContexts()
 149     {
 150         assert(_numContexts == (int)threadContexts.size());
 151         return _numContexts;
 152     }
 153
 154     /** Return number of running (non-halted) thread contexts in
 155      * system.  These threads could be Active or Suspended. */
 156     int numRunningContexts();
 157
 158     Addr pagePtr;
 159
 160     uint64_t init_param;
 161
 162     /** Port to physical memory used for writing object files into ram at
 163      * boot.*/
 164     PortProxy physProxy;
 165     FSTranslatingPortProxy virtProxy;
 166
 167     /** kernel symbol table */
 168     SymbolTable *kernelSymtab;
 169
 170     /** Object pointer for the kernel code */
 171     ObjectFile *kernel;
 172
 173     /** Begining of kernel code */
 174     Addr kernelStart;
 175
 176     /** End of kernel code */
 177     Addr kernelEnd;
 178
 179     /** Entry point in the kernel to start at */
 180     Addr kernelEntry;
 181
 182     /** Mask that should be anded for binary/symbol loading.
 183      * This allows one two different OS requirements for the same ISA to be
 184      * handled.  Some OSes are compiled for a virtual address and need to be
 185      * loaded into physical memory that starts at address 0, while other
 186      * bare metal tools generate images that start at address 0.
 187      */
 188     Addr loadAddrMask;
 189
 190   protected:
 191     uint64_t nextPID;
 192
 193   public:
 194     uint64_t allocatePID()
 195     {
 196         return nextPID++;
 197     }
 198
 199     /** Get a pointer to access the physical memory of the system */
 200     PhysicalMemory& getPhysMem() { return physmem; }
 201
 202     /** Amount of physical memory that is still free */
 203     Addr freeMemSize() const;
 204
 205     /** Amount of physical memory that exists */
 206     Addr memSize() const;
 207
 208     /**
 209      * Check if a physical address is within a range of a memory that
 210      * is part of the global address map.
 211      *
 212      * @param addr A physical address
 213      * @return Whether the address corresponds to a memory
 214      */
 215     bool isMemAddr(Addr addr) const;
 216
 217   protected:
 218
 219     PhysicalMemory physmem;
 220
 221     Enums::MemoryMode memoryMode;
 222     uint64_t workItemsBegin;
 223     uint64_t workItemsEnd;
 224     uint32_t numWorkIds;
 225     std::vector<bool> activeCpus;
 226
 227     /** This array is a per-sytem list of all devices capable of issuing a
 228      * memory system request and an associated string for each master id.
 229      * It's used to uniquely id any master in the system by name for things
 230      * like cache statistics.
 231      */
 232     std::vector<std::string> masterIds;
 233
 234   public:
 235
 236     /** Request an id used to create a request object in the system. All objects
 237      * that intend to issues requests into the memory system must request an id
 238      * in the init() phase of startup. All master ids must be fixed by the
 239      * regStats() phase that immediately preceeds it. This allows objects in the
 240      * memory system to understand how many masters may exist and
 241      * appropriately name the bins of their per-master stats before the stats
 242      * are finalized
 243      */
 244     MasterID getMasterId(std::string req_name);
 245
 246     /** Get the name of an object for a given request id.
 247      */
 248     std::string getMasterName(MasterID master_id);
 249
 250     /** Get the number of masters registered in the system */
 251     MasterID maxMasters()
 252     {
 253         return masterIds.size();
 254     }
 255
 256     virtual void regStats();
 257     /**
 258      * Called by pseudo_inst to track the number of work items started by this
 259      * system.
 260      */
 261     uint64_t
 262     incWorkItemsBegin()
 263     {
 264         return ++workItemsBegin;
 265     }
 266
 267     /**
 268      * Called by pseudo_inst to track the number of work items completed by
 269      * this system.
 270      */
 271     uint64_t
 272     incWorkItemsEnd()
 273     {
 274         return ++workItemsEnd;
 275     }
 276
 277     /**
 278      * Called by pseudo_inst to mark the cpus actively executing work items.
 279      * Returns the total number of cpus that have executed work item begin or
 280      * ends.
 281      */
 282     int
 283     markWorkItem(int index)
 284     {
 285         int count = 0;
 286         assert(index < activeCpus.size());
 287         activeCpus[index] = true;
 288         for (std::vector<bool>::iterator i = activeCpus.begin();
 289              i < activeCpus.end(); i++) {
 290             if (*i) count++;
 291         }
 292         return count;
 293     }
 294
 295     inline void workItemBegin(uint32_t tid, uint32_t workid)
 296     {
 297         std::pair<uint32_t,uint32_t> p(tid, workid);
 298         lastWorkItemStarted[p] = curTick();
 299     }
 300
 301     void workItemEnd(uint32_t tid, uint32_t workid);
 302
 303     /**
 304      * Fix up an address used to match PCs for hooking simulator
 305      * events on to target function executions.  See comment in
 306      * system.cc for details.
 307      */
 308     virtual Addr fixFuncEventAddr(Addr addr)
 309     {
 310         panic("Base fixFuncEventAddr not implemented.\n");
 311     }
 312
 313     /**
 314      * Add a function-based event to the given function, to be looked
 315      * up in the specified symbol table.
 316      */
 317     template <class T>
 318     T *addFuncEvent(SymbolTable *symtab, const char *lbl)
 319     {
 320         Addr addr = 0; // initialize only to avoid compiler warning
 321
 322         if (symtab->findAddress(lbl, addr)) {
 323             T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr));
 324             return ev;
 325         }
 326
 327         return NULL;
 328     }
 329
 330     /** Add a function-based event to kernel code. */
 331     template <class T>
 332     T *addKernelFuncEvent(const char *lbl)
 333     {
 334         return addFuncEvent<T>(kernelSymtab, lbl);
 335     }
 336
 337   public:
 338     std::vector<BaseRemoteGDB *> remoteGDB;
 339     std::vector<GDBListener *> gdbListen;
 340     bool breakpoint();
 341
 342   public:
 343     typedef SystemParams Params;
 344
 345   protected:
 346     Params *_params;
 347
 348   public:
 349     System(Params *p);
 350     ~System();
 351
 352     void initState();
 353
 354     const Params *params() const { return (const Params *)_params; }
 355
 356   public:
 357
 358     /**
 359      * Returns the addess the kernel starts at.
 360      * @return address the kernel starts at
 361      */
 362     Addr getKernelStart() const { return kernelStart; }
 363
 364     /**
 365      * Returns the addess the kernel ends at.
 366      * @return address the kernel ends at
 367      */
 368     Addr getKernelEnd() const { return kernelEnd; }
 369
 370     /**
 371      * Returns the addess the entry point to the kernel code.
 372      * @return entry point of the kernel code
 373      */
 374     Addr getKernelEntry() const { return kernelEntry; }
 375
 376     /// Allocate npages contiguous unused physical pages
 377     /// @return Starting address of first page
 378     Addr allocPhysPages(int npages);
 379
 380     int registerThreadContext(ThreadContext *tc, int assigned=-1);
 381     void replaceThreadContext(ThreadContext *tc, int context_id);
 382
 383     void serialize(std::ostream &os);
 384     void unserialize(Checkpoint *cp, const std::string &section);
 385     virtual void resume();
 386
 387   public:
 388     Counter totalNumInsts;
 389     EventQueue instEventQueue;
 390     std::map<std::pair<uint32_t,uint32_t>, Tick>  lastWorkItemStarted;
 391     std::map<uint32_t, Stats::Histogram*> workItemStats;
 392
 393     ////////////////////////////////////////////
 394     //
 395     // STATIC GLOBAL SYSTEM LIST
 396     //
 397     ////////////////////////////////////////////
 398
 399     static std::vector<System *> systemList;
 400     static int numSystemsRunning;
 401
 402     static void printSystems();
 403
 404     // For futex system call
 405     std::map<uint64_t, std::list<ThreadContext *> * > futexMap;
 406
 407   protected:
 408
 409     /**
 410      * If needed, serialize additional symbol table entries for a
 411      * specific subclass of this sytem. Currently this is used by
 412      * Alpha and MIPS.
 413      *
 414      * @param os stream to serialize to
 415      */
 416     virtual void serializeSymtab(std::ostream &os) {}
 417
 418     /**
 419      * If needed, unserialize additional symbol table entries for a
 420      * specific subclass of this system.
 421      *
 422      * @param cp checkpoint to unserialize from
 423      * @param section relevant section in the checkpoint
 424      */
 425     virtual void unserializeSymtab(Checkpoint *cp,
 426                                    const std::string &section) {}
 427
 428 };
 429
 430 #endif // __SYSTEM_HH__