2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
54 #include "base/loader/symtab.hh"
55 #include "base/misc.hh"
56 #include "base/statistics.hh"
57 #include "cpu/pc_event.hh"
58 #include "enums/MemoryMode.hh"
59 #include "kern/system_events.hh"
60 #include "mem/mem_object.hh"
61 #include "mem/port.hh"
62 #include "mem/port_proxy.hh"
63 #include "mem/physical.hh"
64 #include "params/System.hh"
73 class System : public MemObject
78 * Private class for the system port which is only used as a
79 * master for debug access and for non-structural entities that do
80 * not have a port of their own.
82 class SystemPort : public MasterPort
87 * Create a system port with a name and an owner.
89 SystemPort(const std::string &_name, MemObject *_owner)
90 : MasterPort(_name, _owner)
92 bool recvTimingResp(PacketPtr pkt)
93 { panic("SystemPort does not receive timing!\n"); return false; }
95 { panic("SystemPort does not expect retry!\n"); }
98 SystemPort _systemPort;
103 * After all objects have been created and all ports are
104 * connected, check that the system port is connected.
109 * Get a reference to the system port that can be used by
110 * non-structural simulation objects like processes or threads, or
111 * external entities like loaders and debuggers, etc, to access
114 * @return a reference to the system port we own
116 MasterPort& getSystemPort() { return _systemPort; }
119 * Additional function to return the Port of a memory object.
121 BaseMasterPort& getMasterPort(const std::string &if_name,
122 PortID idx = InvalidPortID);
124 static const char *MemoryModeStrings[4];
128 * Is the system in atomic mode?
130 * There are currently two different atomic memory modes:
131 * 'atomic', which supports caches; and 'atomic_noncaching', which
132 * bypasses caches. The latter is used by hardware virtualized
133 * CPUs. SimObjects are expected to use Port::sendAtomic() and
134 * Port::recvAtomic() when accessing memory in this mode.
136 bool isAtomicMode() const {
137 return memoryMode == Enums::atomic ||
138 memoryMode == Enums::atomic_noncaching;
142 * Is the system in timing mode?
144 * SimObjects are expected to use Port::sendTiming() and
145 * Port::recvTiming() when accessing memory in this mode.
147 bool isTimingMode() const {
148 return memoryMode == Enums::timing;
152 * Should caches be bypassed?
154 * Some CPUs need to bypass caches to allow direct memory
155 * accesses, which is required for hardware virtualization.
157 bool bypassCaches() const {
158 return memoryMode == Enums::atomic_noncaching;
164 * Get the memory mode of the system.
166 * \warn This should only be used by the Python world. The C++
167 * world should use one of the query functions above
168 * (isAtomicMode(), isTimingMode(), bypassCaches()).
170 Enums::MemoryMode getMemoryMode() const { return memoryMode; }
173 * Change the memory mode of the system.
175 * \warn This should only be called by the Python!
177 * @param mode Mode to change to (atomic/timing/...)
179 void setMemoryMode(Enums::MemoryMode mode);
183 * Get the cache line size of the system.
185 unsigned int cacheLineSize() const { return _cacheLineSize; }
187 #if THE_ISA != NULL_ISA
188 PCEventQueue pcEventQueue;
191 std::vector<ThreadContext *> threadContexts;
194 ThreadContext *getThreadContext(ThreadID tid)
196 return threadContexts[tid];
201 assert(_numContexts == (int)threadContexts.size());
205 /** Return number of running (non-halted) thread contexts in
206 * system. These threads could be Active or Suspended. */
207 int numRunningContexts();
213 /** Port to physical memory used for writing object files into ram at
217 /** kernel symbol table */
218 SymbolTable *kernelSymtab;
220 /** Object pointer for the kernel code */
223 /** Begining of kernel code */
226 /** End of kernel code */
229 /** Entry point in the kernel to start at */
232 /** Mask that should be anded for binary/symbol loading.
233 * This allows one two different OS requirements for the same ISA to be
234 * handled. Some OSes are compiled for a virtual address and need to be
235 * loaded into physical memory that starts at address 0, while other
236 * bare metal tools generate images that start at address 0.
240 /** Offset that should be used for binary/symbol loading.
241 * This further allows more flexibily than the loadAddrMask allows alone in
242 * loading kernels and similar. The loadAddrOffset is applied after the
251 uint64_t allocatePID()
256 /** Get a pointer to access the physical memory of the system */
257 PhysicalMemory& getPhysMem() { return physmem; }
259 /** Amount of physical memory that is still free */
260 Addr freeMemSize() const;
262 /** Amount of physical memory that exists */
263 Addr memSize() const;
266 * Check if a physical address is within a range of a memory that
267 * is part of the global address map.
269 * @param addr A physical address
270 * @return Whether the address corresponds to a memory
272 bool isMemAddr(Addr addr) const;
276 PhysicalMemory physmem;
278 Enums::MemoryMode memoryMode;
280 const unsigned int _cacheLineSize;
282 uint64_t workItemsBegin;
283 uint64_t workItemsEnd;
285 std::vector<bool> activeCpus;
287 /** This array is a per-sytem list of all devices capable of issuing a
288 * memory system request and an associated string for each master id.
289 * It's used to uniquely id any master in the system by name for things
290 * like cache statistics.
292 std::vector<std::string> masterIds;
296 /** Request an id used to create a request object in the system. All objects
297 * that intend to issues requests into the memory system must request an id
298 * in the init() phase of startup. All master ids must be fixed by the
299 * regStats() phase that immediately preceeds it. This allows objects in the
300 * memory system to understand how many masters may exist and
301 * appropriately name the bins of their per-master stats before the stats
304 MasterID getMasterId(std::string req_name);
306 /** Get the name of an object for a given request id.
308 std::string getMasterName(MasterID master_id);
310 /** Get the number of masters registered in the system */
311 MasterID maxMasters()
313 return masterIds.size();
316 virtual void regStats();
318 * Called by pseudo_inst to track the number of work items started by this
324 return ++workItemsBegin;
328 * Called by pseudo_inst to track the number of work items completed by
334 return ++workItemsEnd;
338 * Called by pseudo_inst to mark the cpus actively executing work items.
339 * Returns the total number of cpus that have executed work item begin or
343 markWorkItem(int index)
346 assert(index < activeCpus.size());
347 activeCpus[index] = true;
348 for (std::vector<bool>::iterator i = activeCpus.begin();
349 i < activeCpus.end(); i++) {
355 inline void workItemBegin(uint32_t tid, uint32_t workid)
357 std::pair<uint32_t,uint32_t> p(tid, workid);
358 lastWorkItemStarted[p] = curTick();
361 void workItemEnd(uint32_t tid, uint32_t workid);
364 * Fix up an address used to match PCs for hooking simulator
365 * events on to target function executions. See comment in
366 * system.cc for details.
368 virtual Addr fixFuncEventAddr(Addr addr)
370 panic("Base fixFuncEventAddr not implemented.\n");
375 * Add a function-based event to the given function, to be looked
376 * up in the specified symbol table.
378 * The ...OrPanic flavor of the method causes the simulator to
379 * panic if the symbol can't be found.
381 * @param symtab Symbol table to use for look up.
382 * @param lbl Function to hook the event to.
383 * @param desc Description to be passed to the event.
384 * @param args Arguments to be forwarded to the event constructor.
386 template <class T, typename... Args>
387 T *addFuncEvent(const SymbolTable *symtab, const char *lbl,
388 const std::string &desc, Args... args)
390 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
392 #if THE_ISA != NULL_ISA
393 if (symtab->findAddress(lbl, addr)) {
394 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
395 std::forward<Args>(args)...);
404 T *addFuncEvent(const SymbolTable *symtab, const char *lbl)
406 return addFuncEvent<T>(symtab, lbl, lbl);
409 template <class T, typename... Args>
410 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl,
413 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...));
415 panic("Failed to find symbol '%s'", lbl);
422 * Add a function-based event to a kernel symbol.
424 * These functions work like their addFuncEvent() and
425 * addFuncEventOrPanic() counterparts. The only difference is that
426 * they automatically use the kernel symbol table. All arguments
427 * are forwarded to the underlying method.
429 * @see addFuncEvent()
430 * @see addFuncEventOrPanic()
432 * @param lbl Function to hook the event to.
433 * @param args Arguments to be passed to addFuncEvent
435 template <class T, typename... Args>
436 T *addKernelFuncEvent(const char *lbl, Args... args)
438 return addFuncEvent<T>(kernelSymtab, lbl,
439 std::forward<Args>(args)...);
442 template <class T, typename... Args>
443 T *addKernelFuncEventOrPanic(const char *lbl, Args... args)
445 T *e(addFuncEvent<T>(kernelSymtab, lbl,
446 std::forward<Args>(args)...));
448 panic("Failed to find kernel symbol '%s'", lbl);
454 std::vector<BaseRemoteGDB *> remoteGDB;
455 std::vector<GDBListener *> gdbListen;
459 typedef SystemParams Params;
470 const Params *params() const { return (const Params *)_params; }
475 * Returns the addess the kernel starts at.
476 * @return address the kernel starts at
478 Addr getKernelStart() const { return kernelStart; }
481 * Returns the addess the kernel ends at.
482 * @return address the kernel ends at
484 Addr getKernelEnd() const { return kernelEnd; }
487 * Returns the addess the entry point to the kernel code.
488 * @return entry point of the kernel code
490 Addr getKernelEntry() const { return kernelEntry; }
492 /// Allocate npages contiguous unused physical pages
493 /// @return Starting address of first page
494 Addr allocPhysPages(int npages);
496 int registerThreadContext(ThreadContext *tc, int assigned=-1);
497 void replaceThreadContext(ThreadContext *tc, int context_id);
499 void serialize(std::ostream &os);
500 void unserialize(Checkpoint *cp, const std::string §ion);
502 unsigned int drain(DrainManager *dm);
506 Counter totalNumInsts;
507 EventQueue instEventQueue;
508 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
509 std::map<uint32_t, Stats::Histogram*> workItemStats;
511 ////////////////////////////////////////////
513 // STATIC GLOBAL SYSTEM LIST
515 ////////////////////////////////////////////
517 static std::vector<System *> systemList;
518 static int numSystemsRunning;
520 static void printSystems();
522 // For futex system call
523 std::map<uint64_t, std::list<ThreadContext *> * > futexMap;
528 * If needed, serialize additional symbol table entries for a
529 * specific subclass of this sytem. Currently this is used by
532 * @param os stream to serialize to
534 virtual void serializeSymtab(std::ostream &os) {}
537 * If needed, unserialize additional symbol table entries for a
538 * specific subclass of this system.
540 * @param cp checkpoint to unserialize from
541 * @param section relevant section in the checkpoint
543 virtual void unserializeSymtab(Checkpoint *cp,
544 const std::string §ion) {}
550 #endif // __SYSTEM_HH__