src/sim/tlb.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __SIM_TLB_HH__
  44 #define __SIM_TLB_HH__
  45
  46 #include "base/misc.hh"
  47 #include "mem/request.hh"
  48 #include "sim/fault_fwd.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class ThreadContext;
  52 class Packet;
  53 class Port;
  54
  55 class BaseTLB : public SimObject
  56 {
  57   protected:
  58     BaseTLB(const Params *p)
  59         : SimObject(p)
  60     {}
  61
  62   public:
  63     enum Mode { Read, Write, Execute };
  64
  65   public:
  66     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
  67
  68     /** Get any port that the TLB or hardware table walker needs.
  69      * This is used for migrating port connections during a takeOverFrom()
  70      * call. */
  71     virtual Port*  getPort() { return NULL; }
  72
  73     class Translation
  74     {
  75       public:
  76         virtual ~Translation()
  77         {}
  78
  79         /**
  80          * Signal that the translation has been delayed due to a hw page table
  81          * walk.
  82          */
  83         virtual void markDelayed() = 0;
  84
  85         /*
  86          * The memory for this object may be dynamically allocated, and it may
  87          * be responsible for cleaning itself up which will happen in this
  88          * function. Once it's called, the object is no longer valid.
  89          */
  90         virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
  91                             Mode mode) = 0;
  92     };
  93 };
  94
  95 class GenericTLB : public BaseTLB
  96 {
  97   protected:
  98     GenericTLB(const Params *p)
  99         : BaseTLB(p)
 100     {}
 101
 102   public:
 103     void demapPage(Addr vaddr, uint64_t asn);
 104
 105     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 106     void translateTiming(RequestPtr req, ThreadContext *tc,
 107                          Translation *translation, Mode mode);
 108 };
 109
 110 #endif // __ARCH_SPARC_TLB_HH__