2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #ifndef __SIM_TLB_HH__
44 #define __SIM_TLB_HH__
46 #include "base/misc.hh"
47 #include "mem/request.hh"
48 #include "sim/fault_fwd.hh"
49 #include "sim/sim_object.hh"
54 class BaseTLB : public SimObject
57 BaseTLB(const Params *p)
62 enum Mode { Read, Write, Execute };
65 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
68 * Remove all entries from the TLB
70 virtual void flushAll() = 0;
73 * Get the table walker master port if present. This is used for
74 * migrating port connections during a CPU takeOverFrom()
75 * call. For architectures that do not have a table walker, NULL
76 * is returned, hence the use of a pointer rather than a
79 * @return A pointer to the walker master port or NULL if not present
81 virtual BaseMasterPort* getMasterPort() { return NULL; }
83 void memInvalidate() { flushAll(); }
88 virtual ~Translation()
92 * Signal that the translation has been delayed due to a hw page table
95 virtual void markDelayed() = 0;
98 * The memory for this object may be dynamically allocated, and it may
99 * be responsible for cleaning itself up which will happen in this
100 * function. Once it's called, the object is no longer valid.
102 virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
105 /** This function is used by the page table walker to determine if it
106 * should translate the a pending request or if the underlying request
108 * @ return Is the instruction that requested this translation squashed?
110 virtual bool squashed() const { return false; }
114 class GenericTLB : public BaseTLB
117 GenericTLB(const Params *p)
122 void demapPage(Addr vaddr, uint64_t asn);
124 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
125 void translateTiming(RequestPtr req, ThreadContext *tc,
126 Translation *translation, Mode mode);
129 #endif // __ARCH_SPARC_TLB_HH__