ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
[gem5.git] / src / sim / tlb.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __SIM_TLB_HH__
32 #define __SIM_TLB_HH__
33
34 #include "base/misc.hh"
35 #include "mem/request.hh"
36 #include "sim/faults.hh"
37 #include "sim/sim_object.hh"
38
39 class ThreadContext;
40 class Packet;
41
42 class BaseTLB : public SimObject
43 {
44 protected:
45 BaseTLB(const Params *p)
46 : SimObject(p)
47 {}
48
49 public:
50 enum Mode { Read, Write, Execute };
51
52 public:
53 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
54
55 class Translation
56 {
57 public:
58 virtual ~Translation()
59 {}
60
61 /*
62 * The memory for this object may be dynamically allocated, and it may
63 * be responsible for cleaning itself up which will happen in this
64 * function. Once it's called, the object is no longer valid.
65 */
66 virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
67 Mode mode) = 0;
68 };
69 };
70
71 class GenericTLB : public BaseTLB
72 {
73 protected:
74 GenericTLB(const Params *p)
75 : BaseTLB(p)
76 {}
77
78 public:
79 void demapPage(Addr vaddr, uint64_t asn);
80
81 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
82 void translateTiming(RequestPtr req, ThreadContext *tc,
83 Translation *translation, Mode mode);
84 };
85
86 #endif // __ARCH_SPARC_TLB_HH__