4 from nmigen
import (Module
, Array
, Signal
, Mux
, Elaboratable
, ClockSignal
,
6 from nmigen
.cli
import rtlil
9 class ClockSelect(Elaboratable
):
12 self
.clk_sel_i
= Signal() # clock source selection
13 self
.clk_24_i
= Signal(reset_less
=True) # 24 mhz external incoming
14 self
.pll_clk_i
= Signal(reset_less
=True) # PLL input
15 self
.core_clk_o
= Signal(reset_less
=True) # main core clock (selectable)
17 def elaborate(self
, platform
):
19 comb
, sync
= m
.d
.comb
, m
.d
.sync
21 # set up system, zero and one clocks
22 comb
+= self
.core_clk_o
.eq(Mux(self
.clk_sel_i
,
23 self
.pll_clk_i
, self
.clk_24_i
))
28 return [self
.clk_24_i
, self
.pll_18_o
, self
.clk_sel_i
, self
.core_clk_o
]
31 if __name__
== '__main__':
34 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
35 with
open("test_clk_sel.il", "w") as f
: