src/soc/config/loadstore.py

   1 """ConfigureableLoadStoreUnit and ConfigMemoryPortInterface
   2
   3 allows the type of LoadStoreUnit to be run-time selectable
   4
   5 this allows the same code to be used for both small unit tests
   6 as well as larger ones and so on, without needing large amounts
   7 of unnecessarily-duplicated code
   8 """
   9 from soc.experiment.lsmem import TestMemLoadStoreUnit
  10 from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
  11 from soc.experiment.pi2ls import Pi2LSUI
  12 from soc.experiment.pimem import TestMemoryPortInterface
  13 from soc.minerva.units.loadstore import BareLoadStoreUnit
  14 from soc.fu.mmu.fsm import LoadStore1 # MMU and DCache
  15
  16 class ConfigLoadStoreUnit:
  17     def __init__(self, pspec):
  18         lsidict = {'testmem': TestMemLoadStoreUnit,
  19                    'test_bare_wb': TestSRAMBareLoadStoreUnit,
  20                    'bare_wb': BareLoadStoreUnit,
  21                    'mmu_cache_wb': LoadStore1
  22                   }
  23         lsikls = lsidict[pspec.ldst_ifacetype]
  24         self.lsi = lsikls(pspec)
  25
  26
  27 class ConfigMemoryPortInterface:
  28     def __init__(self, pspec):
  29         self.pspec = pspec
  30         if pspec.ldst_ifacetype == 'testpi':
  31             self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus
  32                                               regwid=pspec.reg_wid) # data bus
  33             return
  34         self.lsmem = ConfigLoadStoreUnit(pspec)
  35         if self.pspec.ldst_ifacetype == 'mmu_cache_wb':
  36             self.pi = self.lsmem.lsi.pi # LoadStore1 already is a PortInterface
  37             return
  38         self.pi = Pi2LSUI("mem", lsui=self.lsmem.lsi,
  39                           addr_wid=pspec.addr_wid, # address range
  40                           mask_wid=pspec.mask_wid, # cache line range
  41                           data_wid=pspec.reg_wid)  # data bus width
  42
  43     def wb_bus(self):
  44         if self.pspec.ldst_ifacetype == 'mmu_cache_wb':
  45             return self.lsmem.lsi.dbus
  46         return self.lsmem.lsi.slavebus
  47
  48     def ports(self):
  49         if self.pspec.ldst_ifacetype == 'testpi':
  50             return self.pi.ports()
  51         return list(self.pi.ports()) + self.lsmem.lsi.ports()