1 """Converted from microwatt core_debug.vhdl to nmigen
3 Provides a DMI (Debug Module Interface) for accessing a Libre-SOC core,
4 compatible with microwatt's same interface.
6 See constants below for addresses and register formats
9 from nmigen
import Elaboratable
, Module
, Signal
, Cat
, Const
, Record
, Array
, Mux
10 from nmutil
.iocontrol
import RecordObject
11 from nmigen
.utils
import log2_int
12 from nmigen
.cli
import rtlil
13 from soc
.config
.state
import CoreState
16 # DMI register addresses
20 NIA
= 0b0010 # NIA register (read only for now)
21 MSR
= 0b0011 # MSR (read only)
22 GSPR_IDX
= 0b0100 # GSPR register index
23 GSPR_DATA
= 0b0101 # GSPR register data
24 LOG_ADDR
= 0b0110 # Log buffer address register
25 LOG_DATA
= 0b0111 # Log buffer data register
26 CR
= 0b1000 # CR (read only)
29 # CTRL register (direct actions, write 1 to act, read back 0)
31 # bit 1 : Core reset (doesn't clear stop)
32 # bit 2 : Icache reset
43 # STAT register (read only)
44 # bit 0 : Core stopping (wait til bit 1 set)
45 # bit 1 : Core stopped
46 # bit 2 : Core terminated (clears with start or reset)
53 class DMIInterface(RecordObject
):
54 def __init__(self
, name
):
55 super().__init
__(name
=name
)
56 self
.addr_i
= Signal(4) # DMI register address
57 self
.din
= Signal(64) # DMI data in (if we=1)
58 self
.dout
= Signal(64) # DMI data out (if we=0)
59 self
.req_i
= Signal() # DMI request valid (stb)
60 self
.we_i
= Signal() # DMI write-enable
61 self
.ack_o
= Signal() # DMI ack request
64 class DbgReg(RecordObject
):
65 def __init__(self
, name
):
66 super().__init
__(name
=name
)
69 self
.addr
= Signal(7) # includes fast SPRs, others?
70 self
.data
= Signal(64)
73 class DbgCRReg(RecordObject
):
74 def __init__(self
, name
):
75 super().__init
__(name
=name
)
78 self
.data
= Signal(32)
81 class CoreDebug(Elaboratable
):
82 def __init__(self
, LOG_LENGTH
=0): # TODO - debug log 512):
83 # Length of log buffer
84 self
.LOG_LENGTH
= LOG_LENGTH
85 self
.dmi
= DMIInterface("dmi")
88 self
.core_stop_o
= Signal()
89 self
.core_rst_o
= Signal()
90 self
.icache_rst_o
= Signal()
93 self
.terminate_i
= Signal()
94 self
.core_stopped_i
= Signal()
95 self
.state
= CoreState("core_dbg")
97 # GSPR register read port
98 self
.dbg_gpr
= DbgReg("dbg_gpr")
100 # CR register read port
101 self
.dbg_cr
= DbgReg("dbg_cr")
104 self
.log_data_i
= Signal(256)
105 self
.log_read_addr_i
= Signal(32)
106 self
.log_read_data_o
= Signal(64)
107 self
.log_write_addr_o
= Signal(32)
110 self
.terminated_o
= Signal()
112 def elaborate(self
, platform
):
115 comb
, sync
= m
.d
.comb
, m
.d
.sync
116 dmi
, dbg_gpr
, dbg_cr
= self
.dmi
, self
.dbg_gpr
, self
.dbg_cr
118 # DMI needs fixing... make a one clock pulse
119 dmi_req_i_1
= Signal()
121 # Some internal wires
122 stat_reg
= Signal(64)
124 # Some internal latches
128 do_icreset
= Signal()
129 terminated
= Signal()
130 do_gspr_rd
= Signal()
131 gspr_index
= Signal
.like(dbg_gpr
.addr
)
133 log_dmi_addr
= Signal(32)
134 log_dmi_data
= Signal(64)
135 do_dmi_log_rd
= Signal()
136 dmi_read_log_data
= Signal()
137 dmi_read_log_data_1
= Signal()
139 LOG_INDEX_BITS
= log2_int(self
.LOG_LENGTH
)
141 # Single cycle register accesses on DMI except for GSPR data
142 with m
.Switch(.dmi
.addr_i
):
143 with m
.Case(DBGCore
.GSPR_DATA
):
144 comb
+= dmi
.ack_o
.eq(dbg_gpr
.ack
)
145 comb
+= dbg_gpr
.req
.eq(dmi
.req_i
)
146 with m
.Case(DBGCore
.CR
):
147 comb
+= dmi
.ack_o
.eq(dbg_cr
.ack
)
148 comb
+= dbg_cr
.req
.eq(dmi
.req_i
)
150 comb
+= dmi
.ack_o
.eq(dmi
.req_i
)
152 # Status register read composition (DBUG_CORE_STAT_xxx)
153 comb
+= stat_reg
.eq(Cat(stopping
, # bit 0
154 self
.core_stopped_i
, # bit 1
158 with m
.Switch(dmi
.addr_i
):
159 with m
.Case( DBGCore
.STAT
):
160 comb
+= dmi
.dout
.eq(stat_reg
)
161 with m
.Case( DBGCore
.NIA
):
162 comb
+= dmi
.dout
.eq(self
.state
.pc
)
163 with m
.Case( DBGCore
.MSR
):
164 comb
+= dmi
.dout
.eq(self
.state
.msr
)
165 with m
.Case( DBGCore
.GSPR_DATA
):
166 comb
+= dmi
.dout
.eq(dbg_gpr
.data
)
167 with m
.Case( DBGCore
.LOG_ADDR
):
168 comb
+= dmi
.dout
.eq(Cat(log_dmi_addr
, self
.log_write_addr_o
))
169 with m
.Case( DBGCore
.LOG_DATA
):
170 comb
+= dmi
.dout
.eq(log_dmi_data
)
171 with m
.Case(DBGCore
.CR
):
172 comb
+= dmi
.dout
.eq(dbg_cr
.data
)
175 # Reset the 1-cycle "do" signals
176 sync
+= do_step
.eq(0)
177 sync
+= do_reset
.eq(0)
178 sync
+= do_icreset
.eq(0)
179 sync
+= do_dmi_log_rd
.eq(0)
181 # Edge detect on dmi_req_i for 1-shot pulses
182 sync
+= dmi_req_i_1
.eq(dmi
.req_i
)
183 with m
.If(dmi
.req_i
& ~dmi_req_i_1
):
185 #sync += Display("DMI write to " & to_hstring(dmi_addr))
187 # Control register actions
190 with m
.If(dmi
.addr_i
== DBGCore
.CTRL
):
191 with m
.If(dmi
.din
[DBGCtrl
.RESET
]):
192 sync
+= do_reset
.eq(1)
193 sync
+= terminated
.eq(0)
194 with m
.If(dmi
.din
[DBGCtrl
.STOP
]):
195 sync
+= stopping
.eq(1)
196 with m
.If(dmi
.din
[DBGCtrl
.STEP
]):
197 sync
+= do_step
.eq(1)
198 sync
+= terminated
.eq(0)
199 with m
.If(dmi
.din
[DBGCtrl
.ICRESET
]):
200 sync
+= do_icreset
.eq(1)
201 with m
.If(dmi
.din
[DBGCtrl
.START
]):
202 sync
+= stopping
.eq(0)
203 sync
+= terminated
.eq(0)
206 with m
.Elif(dmi
.addr_i
== DBGCore
.GSPR_IDX
):
207 sync
+= gspr_index
.eq(dmi
.din
)
210 with m
.Elif(dmi
.addr_i
== DBGCore
.LOG_ADDR
):
211 sync
+= log_dmi_addr
.eq(dmi
.din
)
212 sync
+= do_dmi_log_rd
.eq(1)
214 # sync += Display("DMI read from " & to_string(dmi_addr))
217 with m
.Elif(dmi_read_log_data_1
& ~dmi_read_log_data
):
218 # Increment log_dmi_addr after end of read from DBGCore.LOG_DATA
219 lds
= log_dmi_addr
[:LOG_INDEX_BITS
+2]
220 sync
+= lds
.eq(lds
+ 1)
221 sync
+= do_dmi_log_rd
.eq(1)
223 sync
+= dmi_read_log_data_1
.eq(dmi_read_log_data
)
224 sync
+= dmi_read_log_data
.eq(dmi
.req_i
&
225 (dmi
.addr_i
== DBGCore
.LOG_DATA
))
227 # Set core stop on terminate. We'll be stopping some time *after*
228 # the offending instruction, at least until we can do back flushes
229 # that preserve NIA which we can't just yet.
230 with m
.If(self
.terminate_i
):
231 sync
+= stopping
.eq(1)
232 sync
+= terminated
.eq(1)
234 comb
+= dbg_gpr
.addr
.eq(gspr_index
)
236 # Core control signals generated by the debug module
237 comb
+= self
.core_stop_o
.eq(stopping
& ~do_step
)
238 comb
+= self
.core_rst_o
.eq(do_reset
)
239 comb
+= self
.icache_rst_o
.eq(do_icreset
)
240 comb
+= self
.terminated_o
.eq(terminated
)
244 if self
.LOG_LENGTH
== 0:
245 self
.log_read_data_o
.eq(0)
246 self
.log_write_addr_o
.eq(0x00000001)
250 # TODO: debug logging
252 maybe_log: with m.If(LOG_LENGTH > 0 generate
253 subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0)
254 type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0)
255 signal log_array : log_array_t
256 signal log_rd_ptr : log_ptr_t
257 signal log_wr_ptr : log_ptr_t
258 signal log_toggle = Signal()
259 signal log_wr_enable = Signal()
260 signal log_rd_ptr_latched : log_ptr_t
261 signal log_rd = Signal()_vector(255 downto 0)
262 signal log_dmi_reading = Signal()
263 signal log_dmi_read_done = Signal()
265 function select_dword(data = Signal()_vector(255 downto 0)
266 addr = Signal()_vector(31 downto 0)) return std_ulogic_vector is
267 variable firstbit : integer
269 firstbit := to_integer(unsigned(addr(1 downto 0))) * 64
270 return data(firstbit + 63 downto firstbit)
273 attribute ram_style : string
274 attribute ram_style of log_array : signal is "block"
275 attribute ram_decomp : string
276 attribute ram_decomp of log_array : signal is "power"
279 # Use MSB of read addresses to stop the logging
280 log_wr_enable.eq(not (self.log_read_addr(31) or log_dmi_addr(31))
282 log_ram: process(clk)
284 with m.If(rising_edge(clk)):
285 with m.If(log_wr_enable = '1'):
286 log_array(to_integer(log_wr_ptr)).eq(self.log_data
288 log_rd.eq(log_array(to_integer(log_rd_ptr_latched))
293 log_buffer: process(clk)
295 variable data = Signal()_vector(255 downto 0)
297 with m.If(rising_edge(clk)):
298 with m.If(rst = '1'):
299 log_wr_ptr.eq((others => '0')
301 with m.Elif(log_wr_enable = '1'):
302 with m.If(log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS)):
303 log_toggle.eq(not log_toggle
305 log_wr_ptr.eq(log_wr_ptr + 1
307 with m.If(do_dmi_log_rd = '1'):
308 log_rd_ptr_latched.eq(unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2))
310 log_rd_ptr_latched.eq(unsigned(self.log_read_addr(LOG_INDEX_BITS + 1 downto 2))
312 with m.If(log_dmi_read_done = '1'):
313 log_dmi_data.eq(select_dword(log_rd, log_dmi_addr)
315 self.log_read_data.eq(select_dword(log_rd, self.log_read_addr)
317 log_dmi_read_done.eq(log_dmi_reading
318 log_dmi_reading.eq(do_dmi_log_rd
321 self.log_write_addr(LOG_INDEX_BITS - 1 downto 0).eq(std_ulogic_vector(log_wr_ptr)
322 self.log_write_addr(LOG_INDEX_BITS).eq('1'
323 self.log_write_addr(31 downto LOG_INDEX_BITS + 1).eq((others => '0')
330 yield self
.core_stop_o
331 yield self
.core_rst_o
332 yield self
.icache_rst_o
333 yield self
.terminate_i
334 yield self
.core_stopped_i
335 yield from self
.state
336 yield from self
.dbg_gpr
337 yield self
.log_data_i
338 yield self
.log_read_addr_i
339 yield self
.log_read_data_o
340 yield self
.log_write_addr_o
341 yield self
.terminated_o
350 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
351 with
open("test_core_debug.il", "w") as f
:
354 if __name__
== '__main__':