1 # SPDX-License: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
13 from enum
import Enum
, unique
16 from os
.path
import dirname
, join
17 from collections
import namedtuple
21 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
22 basedir
= dirname(dirname(dirname(filedir
)))
23 tabledir
= join(basedir
, 'libreriscv')
24 tabledir
= join(tabledir
, 'openpower')
25 return join(tabledir
, 'isatables')
28 def find_wiki_file(name
):
29 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
30 basedir
= dirname(dirname(dirname(filedir
)))
31 tabledir
= join(basedir
, 'libreriscv')
32 tabledir
= join(tabledir
, 'openpower')
33 tabledir
= join(tabledir
, 'isatables')
35 return join(find_wiki_dir(), name
)
39 file_path
= find_wiki_file(name
)
40 with
open(file_path
, 'r') as csvfile
:
41 reader
= csv
.DictReader(csvfile
)
45 # names of the fields in the tables that don't correspond to an enum
46 single_bit_flags
= ['inv A', 'inv out',
47 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
48 'sgn', 'lk', 'sgl pipe']
50 # default values for fields in the table
51 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
52 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
56 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
59 def get_signal_name(name
):
62 return name
.lower().replace(' ', '_')
64 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
65 # is to process and guard the operation. they are roughly divided by having
66 # the same register input/output signature (X-Form, etc.)
83 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
118 SVL
= 29 # Simple-V for setvl instruction
120 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
144 Idx_1_2
= 5 # due to weird BA/BB for crops
148 class SVP64PredMode(Enum
):
155 class SVP64PredInt(Enum
):
167 class SVP64PredCR(Enum
):
179 class SVP64RMMode(Enum
):
188 class SVP64width(Enum
):
196 class SVP64subvl(Enum
):
204 class SVP64sat(Enum
):
210 # supported instructions: make sure to keep up-to-date with CSV files
211 # just like everything else
213 "NONE", "add", "addc", "addco", "adde", "addeo", "addi", "addic", "addic.",
214 "addis", "addme", "addmeo", "addo", "addze", "addzeo", "and", "andc",
215 "andi.", "andis.", "attn", "b", "bc", "bcctr", "bclr", "bctar",
216 "bpermd", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
217 "cntlzd", "cntlzw", "cnttzd", "cnttzw", "crand", "crandc", "creqv",
218 "crnand", "crnor", "cror", "crorc", "crxor", "darn", "dcbf", "dcbst",
219 "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu",
220 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
221 "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb",
222 "extsh", "extsw", "extswsli", "hrfid", "icbi", "icbt", "isel", "isync",
223 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
224 "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
225 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
226 "lwax", "lwbrx", "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
227 "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
228 "moduw", "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr", "mulhd", "mulhdu",
229 "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
230 "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
231 "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
232 "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
234 "setvl", # https://libre-soc.org/openpower/sv/setvl
235 "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
236 "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
237 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
238 "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
239 "stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
240 "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
241 "tdi", "tlbie", "tlbiel", "tw", "twi", "xor", "xori", "xoris",
244 # two-way lookup of instruction-to-index and vice-versa
247 for i
, insn
in enumerate(_insns
):
251 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
256 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
338 RS
= 4 # for some ALU/Logical operations
356 RS
= 13 # for shiftrot (M-Form)
363 RB
= 2 # for shiftrot (M-Form)
385 class LDSTMode(Enum
):
420 class CROutSel(Enum
):
429 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
430 # http://libre-riscv.org/openpower/isatables/sprs.csv
431 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
433 spr_csv
= get_csv("sprs.csv")
434 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
438 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
439 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
441 spr_dict
[int(row
['Idx'])] = info
442 spr_byname
[row
['SPR']] = info
443 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
444 SPR
= Enum('SPR', fields
)
455 if __name__
== '__main__':
456 # find out what the heck is in SPR enum :)
457 print("sprs", len(SPR
))
460 print(SPR
.__members
__['TAR'])
462 print(x
, x
.value
, str(x
), x
.name
)
464 print("function", Function
.ALU
.name
)