1 from collections
import OrderedDict
2 from soc
.decoder
.power_fields
import DecodeFields
, BitRange
3 from nmigen
import Module
, Elaboratable
, Signal
, Cat
4 from nmigen
.cli
import rtlil
5 from copy
import deepcopy
8 class SignalBitRange(BitRange
):
9 def __init__(self
, signal
):
10 BitRange
.__init
__(self
)
13 def __deepcopy__(self
, memo
):
14 signal
= deepcopy(self
.signal
, memo
)
15 retval
= SignalBitRange(signal
=signal
)
16 for k
, v
in self
.items():
23 width
= self
.signal
.width
26 def __getitem__(self
, subs
):
27 # *sigh* field numberings are bit-inverted. PowerISA 3.0B section 1.3.2
28 if isinstance(subs
, slice):
30 start
, stop
, step
= subs
.start
, subs
.stop
, subs
.step
38 start
= len(self
) + start
+ 1
40 stop
= len(self
) + stop
+ 1
41 for t
in range(start
, stop
, step
):
42 t
= len(self
) - 1 - t
# invert field back
43 k
= OrderedDict
.__getitem
__(self
, t
)
44 res
.append(self
.signal
[self
._rev
(k
)]) # reverse-order here
48 subs
= len(self
) + subs
49 subs
= len(self
) - 1 - subs
# invert field back
50 k
= OrderedDict
.__getitem
__(self
, subs
)
51 return self
.signal
[self
._rev
(k
)] # reverse-order here
54 class SigDecode(Elaboratable
):
56 def __init__(self
, width
):
57 self
.opcode_in
= Signal(width
, reset_less
=False)
58 self
.df
= DecodeFields(SignalBitRange
, [self
.opcode_in
])
59 self
.df
.create_specs()
61 def elaborate(self
, platform
):
67 return [self
.opcode_in
]
70 def create_sigdecode():
75 if __name__
== '__main__':
76 sigdecode
= create_sigdecode()
77 vl
= rtlil
.convert(sigdecode
, ports
=sigdecode
.ports())
78 with
open("decoder.il", "w") as f
: