3 based on Anton Blanchard microwatt dcache.vhdl
7 from enum
import Enum
, unique
9 from nmigen
import Module
, Signal
, Elaboratable
,
11 from nmigen
.cli
import main
12 from nmigen
.iocontrol
import RecordObject
13 from nmigen
.util
import log2_int
15 from experiment
.mem_types
import LoadStore1ToDcacheType
,
16 DcacheToLoadStore1Type
,
20 from experiment
.wb_types
import WB_ADDR_BITS
, WB_DATA_BITS
, WB_SEL_BITS
,
21 WBAddrType
, WBDataType
, WBSelType
,
22 WbMasterOut
, WBSlaveOut
,
23 WBMasterOutVector
, WBSlaveOutVector
,
24 WBIOMasterOut
, WBIOSlaveOut
27 # Record for storing permission, attribute, etc. bits from a PTE
28 class PermAttr(RecordObject
):
31 self
.reference
= Signal()
32 self
.changed
= Signal()
33 self
.nocache
= Signal()
35 self
.rd_perm
= Signal()
36 self
.wr_perm
= Signal()
39 def extract_perm_attr(pte
):
50 # Type of operation on a "valid" input
54 OP_BAD
= 1 # NC cache hit, TLB miss, prot/RC failure
55 OP_STCX_FAIL
= 2 # conditional store w/o reservation
56 OP_LOAD_HIT
= 3 # Cache hit on load
57 OP_LOAD_MISS
= 4 # Load missing cache
58 OP_LOAD_NC
= 5 # Non-cachable load
59 OP_STORE_HIT
= 6 # Store hitting cache
60 OP_STORE_MISS
= 7 # Store missing cache
66 IDLE
= 0 # Normal load hit processing
67 RELOAD_WAIT_ACK
= 1 # Cache reload wait ack
68 STORE_WAIT_ACK
= 2 # Store wait ack
69 NC_LOAD_WAIT_ACK
= 3 # Non-cachable load wait ack
74 # In order to make timing, we use the BRAMs with
75 # an output buffer, which means that the BRAM
76 # output is delayed by an extra cycle.
78 # Thus, the dcache has a 2-stage internal pipeline
79 # for cache hits with no stalls.
81 # All other operations are handled via stalling
84 # The second stage can thus complete a hit at the same
85 # time as the first stage emits a stall for a complex op.
87 # Stage 0 register, basically contains just the latched request
88 class RegStage0(RecordObject
):
91 self
.req
= LoadStore1ToDcacheType()
95 self
.mmu_req
= Signal() # indicates source of request
98 class MemAccessRequest(RecordObject
):
102 self
.valid
= Signal()
104 self
.real_addr
= Signal(REAL_ADDR_BITS
)
105 self
.data
= Signal(64)
106 self
.byte_sel
= Signal(8)
107 self
.hit_way
= Signal(WAY_BITS
)
108 self
.same_tag
= Signal()
109 self
.mmu_req
= Signal()
112 # First stage register, contains state for stage 1 of load hits
113 # and for the state machine used by all other operations
114 class RegStage1(RecordObject
):
117 # Info about the request
118 self
.full
= Signal() # have uncompleted request
119 self
.mmu_req
= Signal() # request is from MMU
120 self
.req
= MemAccessRequest()
123 self
.hit_way
= Signal(WAY_BITS
)
124 self
.hit_load_valid
= Signal()
125 self
.hit_index
= Signal(INDEX
)
126 self
.cache_hit
= Signal()
129 self
.tlb_hit
= Signal()
130 self
.tlb_hit_way
= Signal(TLB_WAY
)
131 self
.tlb_hit_index
= Signal(TLB_SET_SIZE
)
133 # 2-stage data buffer for data forwarded from writes to reads
134 self
.forward_data1
= Signal(64)
135 self
.forward_data2
= Signal(64)
136 self
.forward_sel1
= Signal(8)
137 self
.forward_valid1
= Signal()
138 self
.forward_way1
= Signal(WAY_BITS
)
139 self
.forward_row1
= Signal(ROW
)
140 self
.use_forward1
= Signal()
141 self
.forward_sel
= Signal(8)
143 # Cache miss state (reload state machine)
146 self
.write_bram
= Signal()
147 self
.write_tag
= Signal()
148 self
.slow_valid
= Signal()
149 self
.wb
= WishboneMasterOut()
150 self
.reload_tag
= Signal(CACHE_TAG
)
151 self
.store_way
= Signal(WAY_BITS
)
152 self
.store_row
= Signal(ROW
)
153 self
.store_index
= Signal(INDEX
)
154 self
.end_row_ix
= Signal(ROW_IN_LINE
)
155 self
.rows_valid
= RowPerLineValidArray()
156 self
.acks_pending
= Signal(3)
157 self
.inc_acks
= Signal()
158 self
.dec_acks
= Signal()
160 # Signals to complete (possibly with error)
161 self
.ls_valid
= Signal()
162 self
.ls_error
= Signal()
163 self
.mmu_done
= Signal()
164 self
.mmu_error
= Signal()
165 self
.cache_paradox
= Signal()
167 # Signal to complete a failed stcx.
168 self
.stcx_fail
= Signal()
171 # Reservation information
172 class Reservation(RecordObject
):
176 # TODO LINE_OFF_BITS is 6
177 addr
= Signal(63 downto LINE_OFF_BITS
)
180 # Set associative dcache write-through
182 # TODO (in no specific order):
184 # * See list in icache.vhdl
185 # * Complete load misses on the cycle when WB data comes instead of
186 # at the end of line (this requires dealing with requests coming in
188 class Dcache(Elaboratable
):
190 # TODO: make these parameters of Dcache at some point
191 self
.LINE_SIZE
= 64 # Line size in bytes
192 self
.NUM_LINES
= 32 # Number of lines in a set
193 self
.NUM_WAYS
= 4 # Number of ways
194 self
.TLB_SET_SIZE
= 64 # L1 DTLB entries per set
195 self
.TLB_NUM_WAYS
= 2 # L1 DTLB number of sets
196 self
.TLB_LG_PGSZ
= 12 # L1 DTLB log_2(page_size)
197 self
.LOG_LENGTH
= 0 # Non-zero to enable log data collection
199 self
.d_in
= LoadStore1ToDcacheType()
200 self
.d_out
= DcacheToLoadStore1Type()
202 self
.m_in
= MmuToDcacheType()
203 self
.m_out
= DcacheToMmuType()
205 self
.stall_out
= Signal()
207 self
.wb_out
= WBMasterOut()
208 self
.wb_in
= WBSlaveOut()
210 self
.log_out
= Signal(20)
212 # Latch the request in r0.req as long as we're not stalling
213 def stage_0(self
, m
, d_in
, m_in
):
217 # variable r : reg_stage_0_t;
222 # if rising_edge(clk) then
223 # assert (d_in.valid and m_in.valid) = '0'
224 # report "request collision loadstore vs MMU";
225 assert ~
(d_in
.valid
& m_in
.valid
) "request collision
228 # if m_in.valid = '1' then
229 with m
.If(m_in
.valid
):
230 # r.req.valid := '1';
231 # r.req.load := not (m_in.tlbie or m_in.tlbld);
234 # r.req.reserve := '0';
235 # r.req.virt_mode := '0';
236 # r.req.priv_mode := '1';
237 # r.req.addr := m_in.addr;
238 # r.req.data := m_in.pte;
239 # r.req.byte_sel := (others => '1');
240 # r.tlbie := m_in.tlbie;
241 # r.doall := m_in.doall;
242 # r.tlbld := m_in.tlbld;
244 sync
+= r
.req
.valid
.eq(1)
245 sync
+= r
.req
.load
.eq(~
(m_in
.tlbie | m_in
.tlbld
))
246 sync
+= r
.req
.priv_mode
.eq(1)
247 sync
+= r
.req
.addr
.eq(m_in
.addr
)
248 sync
+= r
.req
.data
.eq(m_in
.pte
)
249 sync
+= r
.req
.byte_sel
.eq(1)
250 sync
+= r
.tlbie
.eq(m_in
.tlbie
)
251 sync
+= r
.doall
.eq(m_in
.doall
)
252 sync
+= r
.tlbld
.eq(m_in
.tlbld
)
253 sync
+= r
.mmu_req
.eq(1)
261 sync
+= r
.req
.eq(d_in
)
265 # elsif r1.full = '0' or r0_full = '0' then
266 with m
.If(~r1
.full | ~r0_full
):
268 # r0_full <= r.req.valid;
270 sync
+= r0_full
.eq(r
.req
.valid
)
276 # Operates in the second cycle on the request latched in r0.req.
277 # TLB updates write the entry at the end of the second cycle.
278 def tlb_read(self
, m
, m_in
, d_in
, r0_stall
, tlb_valid_way
,
279 tlb_tag_way
, tlb_pte_way
, dtlb_valid_bits
,
280 dtlb_tags
, dtlb_ptes
):
285 # variable index : tlb_index_t;
286 # variable addrbits :
287 # std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
289 addrbits
= Signal(TLB_SET_BITS
)
295 # if rising_edge(clk) then
296 # if m_in.valid = '1' then
297 with m
.If(m_in
.valid
):
298 # addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
299 # - 1 downto TLB_LG_PGSZ);
300 sync
+= addrbits
.eq(m_in
.addr
[
301 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
305 # addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
306 # - 1 downto TLB_LG_PGSZ);
307 sync
+= addrbits
.eq(d_in
.addr
[
308 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
312 # index := to_integer(unsigned(addrbits));
313 sync
+= index
.eq(addrbits
)
314 # -- If we have any op and the previous op isn't
315 # -- finished, then keep the same output for next cycle.
316 # if r0_stall = '0' then
317 # If we have any op and the previous op isn't finished,
318 # then keep the same output for next cycle.
319 with m
.If(~r0_stall
):
320 sync
+= tlb_valid_way
.eq(dtlb_valid_bits
[index
])
321 sync
+= tlb_tag_way
.eq(dtlb_tags
[index
])
322 sync
+= tlb_pte_way
.eq(dtlb_ptes
[index
])
327 # -- Generate TLB PLRUs
328 # maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
330 def maybe_tlb_plrus(self
, m
, r1
, tlb_plru_victim
):
334 with m
.If(TLB_NUM_WAYS
> 1):
336 # TODO understand how to conver generate statements
337 # tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
338 # -- TLB PLRU interface
339 # signal tlb_plru_acc :
340 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
341 # signal tlb_plru_acc_en : std_ulogic;
342 # signal tlb_plru_out :
343 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
345 # tlb_plru : entity work.plru
347 # BITS => TLB_WAY_BITS
352 # acc => tlb_plru_acc,
353 # acc_en => tlb_plru_acc_en,
354 # lru => tlb_plru_out
360 # if r1.tlb_hit_index = i then
361 # tlb_plru_acc_en <= r1.tlb_hit;
363 # tlb_plru_acc_en <= '0';
366 # std_ulogic_vector(to_unsigned(
367 # r1.tlb_hit_way, TLB_WAY_BITS
369 # tlb_plru_victim(i) <= tlb_plru_out;
375 def tlb_search(self
, tlb_req_index
, r0
, tlb_valid_way_ tlb_tag_way
,
376 tlb_pte_way
, pte
, tlb_hit
, valid_ra
, perm_attr
, ra
):
381 # variable hitway : tlb_way_t;
382 # variable hit : std_ulogic;
383 # variable eatag : tlb_tag_t;
394 # to_integer(unsigned(r0.req.addr(
395 # TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ
399 # eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
400 # for i in tlb_way_t loop
401 # if tlb_valid_way(i) = '1' and
402 # read_tlb_tag(i, tlb_tag_way) = eatag then
407 # tlb_hit <= hit and r0_valid;
408 # tlb_hit_way <= hitway;
409 comb
+= tlb_req_index
.eq(r0
.req
.addr
[
410 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
413 comb
+= eatag
.eq(r0
.req
.addr
[
414 TLB_LG_PGSZ
+ TLB_SET_BITS
:64
418 with m
.If(tlb_valid_way(i
)
419 & read_tlb_tag(i
, tlb_tag_way
) == eatag
):
424 comb
+= tlb_hit
.eq(hit
& r0_valid
)
425 comb
+= tlb_hit_way
.eq(hitway
)
427 # if tlb_hit = '1' then
429 # pte <= read_tlb_pte(hitway, tlb_pte_way);
430 comb
+= pte
.eq(read_tlb_pte(hitway
, tlb_pte_way
))
433 # pte <= (others => '0');
436 # valid_ra <= tlb_hit or not r0.req.virt_mode;
437 comb
+= valid_ra
.eq(tlb_hit | ~r0
.req
.virt_mode
)
438 # if r0.req.virt_mode = '1' then
439 with m
.If(r0
.req
.virt_mode
):
440 # ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
441 # r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
442 # (ROW_OFF_BITS-1 downto 0 => '0');
443 # perm_attr <= extract_perm_attr(pte);
445 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
446 r0
.req
.addr
[ROW_OFF_BITS
:TLB_LG_PGSZ
],
447 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
449 comb
+= perm_attr
.eq(extract_perm_attr(pte
))
453 # REAL_ADDR_BITS - 1 downto ROW_OFF_BITS
454 # ) & (ROW_OFF_BITS-1 downto 0 => '0');
456 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
457 r0
.rq
.addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
]
460 # perm_attr <= real_mode_perm_attr;
461 comb
+= perm_attr
.reference
.eq(1)
462 comb
+= perm_attr
.changed
.eq(1)
463 comb
+= perm_attr
.priv
.eq(1)
464 comb
+= perm_attr
.nocache
.eq(0)
465 comb
+= perm_attr
.rd_perm
.eq(1)
466 comb
+= perm_attr
.wr_perm
.eq(1)
470 def tlb_update(self
, r0_valid
, r0
, dtlb_valid_bits
, tlb_req_index
,
471 tlb_hit_way
, tlb_hit
, tlb_plru_victim
, tlb_tag_way
,
472 dtlb_tags
, tlb_pte_way
, dtlb_ptes
, dtlb_valid_bits
):
477 # variable tlbie : std_ulogic;
478 # variable tlbwe : std_ulogic;
479 # variable repl_way : tlb_way_t;
480 # variable eatag : tlb_tag_t;
481 # variable tagset : tlb_way_tags_t;
482 # variable pteset : tlb_way_ptes_t;
487 tagset
= TLBWayTags()
488 pteset
= TLBWayPtes()
498 # if rising_edge(clk) then
499 # tlbie := r0_valid and r0.tlbie;
500 # tlbwe := r0_valid and r0.tlbldoi;
501 sync
+= tlbie
.eq(r0_valid
& r0
.tlbie
)
502 sync
+= tlbwe
.eq(r0_valid
& r0
.tlbldoi
)
504 # if rst = '1' or (tlbie = '1' and r0.doall = '1') then
505 # with m.If (TODO understand how signal resets work in nmigen)
506 # -- clear all valid bits at once
507 # for i in tlb_index_t loop
508 # dtlb_valids(i) <= (others => '0');
510 # clear all valid bits at once
511 for i
in range(TLB_SET_SIZE
):
512 sync
+= dtlb_valid_bits
[i
].eq(0)
513 # elsif tlbie = '1' then
515 # if tlb_hit = '1' then
517 # dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
518 sync
+= dtlb_valid_bits
[tlb_req_index
][tlb_hit_way
].eq(0)
520 # elsif tlbwe = '1' then
522 # if tlb_hit = '1' then
524 # repl_way := tlb_hit_way;
525 sync
+= repl_way
.eq(tlb_hit_way
)
528 # repl_way := to_integer(unsigned(
529 # tlb_plru_victim(tlb_req_index)));
530 sync
+= repl_way
.eq(tlb_plru_victim
[tlb_req_index
])
532 # eatag := r0.req.addr(
533 # 63 downto TLB_LG_PGSZ + TLB_SET_BITS
535 # tagset := tlb_tag_way;
536 # write_tlb_tag(repl_way, tagset, eatag);
537 # dtlb_tags(tlb_req_index) <= tagset;
538 # pteset := tlb_pte_way;
539 # write_tlb_pte(repl_way, pteset, r0.req.data);
540 # dtlb_ptes(tlb_req_index) <= pteset;
541 # dtlb_valids(tlb_req_index)(repl_way) <= '1';
542 sync
+= eatag
.eq(r0
.req
.addr
[TLB_LG_PGSZ
+ TLB_SET_BITS
:64])
543 sync
+= tagset
.eq(tlb_tag_way
)
544 sync
+= write_tlb_tag(repl_way
, tagset
, eatag
)
545 sync
+= dtlb_tags
[tlb_req_index
].eq(tagset
)
546 sync
+= pteset
.eq(tlb_pte_way
)
547 sync
+= write_tlb_pte(repl_way
, pteset
, r0
.req
.data
)
548 sync
+= dtlb_ptes
[tlb_req_index
].eq(pteset
)
549 sync
+= dtlb_valid_bits
[tlb_req_index
][repl_way
].eq(1)
555 # maybe_plrus: if NUM_WAYS > 1 generate
557 def maybe_plrus(self
, r1
):
563 # TODO learn translation of generate into nmgien @lkcl
564 # plrus: for i in 0 to NUM_LINES-1 generate
566 # signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
567 # signal plru_acc_en : std_ulogic;
568 # signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
571 # TODO learn tranlation of entity, generic map, port map in
573 # plru : entity work.plru
581 # acc_en => plru_acc_en,
588 # if r1.hit_index = i then
590 with m
.If(r1
.hit_index
== i
):
591 # plru_acc_en <= r1.cache_hit;
592 comb
+= plru_acc_en
.eq(r1
.cache_hit
)
595 # plru_acc_en <= '0';
596 comb
+= plru_acc_en
.eq(0)
598 # plru_acc <= std_ulogic_vector(to_unsigned(
599 # r1.hit_way, WAY_BITS
601 # plru_victim(i) <= plru_out;
602 comb
+= plru_acc
.eq(r1
.hit_way
)
603 comb
+= plru_victim
[i
].eq(plru_out
)
608 # -- Cache tag RAM read port
609 # cache_tag_read : process(clk)
610 # Cache tag RAM read port
611 def cache_tag_read(self
, r0_stall
, req_index
, m_in
, d_in
,
612 cache_tag_set
, cache_tags
):
617 # variable index : index_t;
618 index
= Signal(INDEX
)
623 # if rising_edge(clk) then
624 # if r0_stall = '1' then
626 # index := req_index;
627 sync
+= index
.eq(req_index
)
629 # elsif m_in.valid = '1' then
630 with m
.Elif(m_in
.valid
):
631 # index := get_index(m_in.addr);
632 sync
+= index
.eq(get_index(m_in
.addr
))
636 # index := get_index(d_in.addr);
637 sync
+= index
.eq(get_index(d_in
.addr
))
639 # cache_tag_set <= cache_tags(index);
640 sync
+= cache_tag_set
.eq(cache_tags
[index
])
644 # Cache request parsing and hit detection
645 def dcache_request(self
, r0
, ra
, req_index
, req_row
, req_tag
,
646 r0_valid
, r1
, cache_valid_bits
, replace_way
,
647 use_forward1_next
, use_forward2_next
,
648 req_hit_way
, plru_victim
, rc_ok
, perm_attr
,
649 valid_ra
, perm_ok
, access_ok
, req_op
, req_ok
,
650 r0_stall
, m_in
, early_req_row
, d_in
):
655 # variable is_hit : std_ulogic;
656 # variable hit_way : way_t;
657 # variable op : op_t;
658 # variable opsel : std_ulogic_vector(2 downto 0);
659 # variable go : std_ulogic;
660 # variable nc : std_ulogic;
661 # variable s_hit : std_ulogic;
662 # variable s_tag : cache_tag_t;
663 # variable s_pte : tlb_pte_t;
664 # variable s_ra : std_ulogic_vector(
665 # REAL_ADDR_BITS - 1 downto 0
667 # variable hit_set : std_ulogic_vector(
668 # TLB_NUM_WAYS - 1 downto 0
670 # variable hit_way_set : hit_way_set_t;
671 # variable rel_matches : std_ulogic_vector(
672 # TLB_NUM_WAYS - 1 downto 0
676 hit_way
= Signal(WAY_BITS
)
682 s_tag
= Signal(CACHE_TAG
)
683 s_pte
= Signal(TLB_PTE
)
684 s_ra
= Signal(REAL_ADDR_BITS
)
685 hit_set
= Signal(TLB_NUM_WAYS
)
686 hit_way_set
= HitWaySet()
687 rel_matches
= Signal(TLB_NUM_WAYS
)
707 # -- Extract line, row and tag from request
708 # req_index <= get_index(r0.req.addr);
709 # req_row <= get_row(r0.req.addr);
710 # req_tag <= get_tag(ra);
712 # go := r0_valid and not (r0.tlbie or r0.tlbld)
713 # and not r1.ls_error;
714 # Extract line, row and tag from request
715 comb
+= req_index
.eq(get_index(r0
.req
.addr
))
716 comb
+= req_row
.eq(get_row(r0
.req
.addr
))
717 comb
+= req_tag
.eq(get_tag(ra
))
719 comb
+= go
.eq(r0_valid
& ~
(r0
.tlbie | r0
.tlbld
) & ~r1
.ls_error
)
724 # Test if pending request is a hit on any way
725 # In order to make timing in virtual mode,
726 # when we are using the TLB, we compare each
727 # way with each of the real addresses from each way of
728 # the TLB, and then decide later which match to use.
729 comb
+= hit_way
.eq(0)
731 comb
+= rel_match
.eq(0)
733 # if r0.req.virt_mode = '1' then
734 with m
.If(r0
.req
.virt_mode
):
735 # rel_matches := (others => '0');
736 comb
+= rel_matches
.eq(0)
737 # for j in tlb_way_t loop
738 for j
in range(TLB_WAY
):
739 # hit_way_set(j) := 0;
741 # s_pte := read_tlb_pte(j, tlb_pte_way);
742 # s_ra := s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ)
743 # & r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
744 # s_tag := get_tag(s_ra);
745 comb
+= hit_way_set
[j
].eq(0)
747 comb
+= s_pte
.eq(read_tlb_pte(j
, tlb_pte_way
))
749 r0
.req
.addr
[0:TLB_LG_PGSZ
],
750 s_pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
752 comb
+= s_tag
.eq(get_tag(s_ra
))
754 # for i in way_t loop
755 for i
in range(NUM_WAYS
):
756 # if go = '1' and cache_valids(req_index)(i) = '1'
757 # and read_tag(i, cache_tag_set) = s_tag
758 # and tlb_valid_way(j) = '1' then
759 with m
.If(go
& cache_valid_bits
[req_index
][i
] &
760 read_tag(i
, cache_tag_set
) == s_tag
762 # hit_way_set(j) := i;
764 comb
+= hit_way_set
[j
].eq(i
)
768 # hit_set(j) := s_hit;
769 comb
+= hit_set
[j
].eq(s_hit
)
770 # if s_tag = r1.reload_tag then
771 with m
.If(s_tag
== r1
.reload_tag
):
772 # rel_matches(j) := '1';
773 comb
+= rel_matches
[j
].eq(1)
776 # if tlb_hit = '1' then
778 # is_hit := hit_set(tlb_hit_way);
779 # hit_way := hit_way_set(tlb_hit_way);
780 # rel_match := rel_matches(tlb_hit_way);
781 comb
+= is_hit
.eq(hit_set
[tlb_hit_way
])
782 comb
+= hit_way
.eq(hit_way_set
[tlb_hit_way
])
783 comb
+= rel_match
.eq(rel_matches
[tlb_hit_way
])
787 # s_tag := get_tag(r0.req.addr);
788 comb
+= s_tag
.eq(get_tag(r0
.req
.addr
))
789 # for i in way_t loop
790 for i
in range(NUM_WAYS
):
791 # if go = '1' and cache_valids(req_index)(i) = '1' and
792 # read_tag(i, cache_tag_set) = s_tag then
793 with m
.If(go
& cache_valid_bits
[req_index
][i
] &
794 read_tag(i
, cache_tag_set
) == s_tag
):
797 comb
+= hit_way
.eq(i
)
801 # if s_tag = r1.reload_tag then
802 with m
.If(s_tag
== r1
.reload_tag
):
804 comb
+= rel_match
.eq(1)
807 # req_same_tag <= rel_match;
808 comb
+= req_same_tag
.eq(rel_match
)
810 # if r1.state = RELOAD_WAIT_ACK and req_index = r1.store_index
811 # and rel_match = '1' then
812 # See if the request matches the line currently being reloaded
813 with m
.If(r1
.state
== State
.RELOAD_WAIT_ACK
& req_index
==
814 r1
.store_index
& rel_match
):
815 # For a store, consider this a hit even if the row isn't
816 # valid since it will be by the time we perform the store.
817 # For a load, check the appropriate row valid bit.
820 # or r1.rows_valid(req_row mod ROW_PER_LINE);
821 # hit_way := replace_way;
822 comb
+= is_hit
.eq(~r0
.req
.load
823 | r1
.rows_valid
[req_row
% ROW_PER_LINE
]
825 comb
+= hit_way
.eq(replace_way
)
828 # -- Whether to use forwarded data for a load or not
829 # Whether to use forwarded data for a load or not
830 # use_forward1_next <= '0';
831 comb
+= use_forward1_next
.eq(0)
832 # if get_row(r1.req.real_addr) = req_row
833 # and r1.req.hit_way = hit_way then
834 with m
.If(get_row(r1
.req
.real_addr
) == req_row
835 & r1
.req
.hit_way
== hit_way
)
836 # Only need to consider r1.write_bram here, since if we
837 # are writing refill data here, then we don't have a
838 # cache hit this cycle on the line being refilled.
839 # (There is the possibility that the load following the
840 # load miss that started the refill could be to the old
841 # contents of the victim line, since it is a couple of
842 # cycles after the refill starts before we see the updated
843 # cache tag. In that case we don't use the bypass.)
844 # use_forward1_next <= r1.write_bram;
845 comb
+= use_forward1_next
.eq(r1
.write_bram
)
847 # use_forward2_next <= '0';
848 comb
+= use_forward2_next
.eq(0)
849 # if r1.forward_row1 = req_row
850 # and r1.forward_way1 = hit_way then
851 with m
.If(r1
.forward_row1
== req_row
852 & r1
.forward_way1
== hit_way
):
853 # use_forward2_next <= r1.forward_valid1;
854 comb
+= use_forward2_next
.eq(r1
.forward_valid1
)
857 # The way that matched on a hit
858 # req_hit_way <= hit_way;
859 comb
+= req_hit_way
.eq(hit_way
)
861 # The way to replace on a miss
862 # if r1.write_tag = '1' then
863 with m
.If(r1
.write_tag
):
864 # replace_way <= to_integer(unsigned(
865 # plru_victim(r1.store_index)
867 replace_way
.eq(plru_victim
[r1
.store_index
])
870 # replace_way <= r1.store_way;
871 comb
+= replace_way
.eq(r1
.store_way
)
874 # work out whether we have permission for this access
875 # NB we don't yet implement AMR, thus no KUAP
876 # rc_ok <= perm_attr.reference and
877 # (r0.req.load or perm_attr.changed);
878 # perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
879 # (perm_attr.wr_perm or (r0.req.load
880 # and perm_attr.rd_perm));
881 # access_ok <= valid_ra and perm_ok and rc_ok;
884 & (r0
.req
.load | perm_attr
.changed
)
886 comb
+= perm_ok
.eq((r0
.req
.prive_mode | ~perm_attr
.priv
)
888 |
(r0
.req
.load
& perm_attr
.rd_perm
)
890 comb
+= access_ok
.eq(valid_ra
& perm_ok
& rc_ok
)
891 # nc := r0.req.nc or perm_attr.nocache;
893 # Combine the request and cache hit status to decide what
894 # operation needs to be done
895 comb
+= nc
.eq(r0
.req
.nc | perm_attr
.nocache
)
896 comb
+= op
.eq(Op
.OP_NONE
)
899 # if access_ok = '0' then
900 with m
.If(~access_ok
):
902 comb
+= op
.eq(Op
.OP_BAD
)
903 # elsif cancel_store = '1' then
904 with m
.Elif(cancel_store
):
905 # op := OP_STCX_FAIL;
906 comb
+= op
.eq(Op
.OP_STCX_FAIL
)
909 # opsel := r0.req.load & nc & is_hit;
910 comb
+= opsel
.eq(Cat(is_hit
, nc
, r0
.req
.load
))
912 with m
.Switch(opsel
):
913 # when "101" => op := OP_LOAD_HIT;
914 # when "100" => op := OP_LOAD_MISS;
915 # when "110" => op := OP_LOAD_NC;
916 # when "001" => op := OP_STORE_HIT;
917 # when "000" => op := OP_STORE_MISS;
918 # when "010" => op := OP_STORE_MISS;
919 # when "011" => op := OP_BAD;
920 # when "111" => op := OP_BAD;
921 # when others => op := OP_NONE;
922 with m
.Case(Const(0b101, 3)):
923 comb
+= op
.eq(Op
.OP_LOAD_HIT
)
925 with m
.Case(Cosnt(0b100, 3)):
926 comb
+= op
.eq(Op
.OP_LOAD_MISS
)
928 with m
.Case(Const(0b110, 3)):
929 comb
+= op
.eq(Op
.OP_LOAD_NC
)
931 with m
.Case(Const(0b001, 3)):
932 comb
+= op
.eq(Op
.OP_STORE_HIT
)
934 with m
.Case(Const(0b000, 3)):
935 comb
+= op
.eq(Op
.OP_STORE_MISS
)
937 with m
.Case(Const(0b010, 3)):
938 comb
+= op
.eq(Op
.OP_STORE_MISS
)
940 with m
.Case(Const(0b011, 3)):
941 comb
+= op
.eq(Op
.OP_BAD
)
943 with m
.Case(Const(0b111, 3)):
944 comb
+= op
.eq(Op
.OP_BAD
)
947 comb
+= op
.eq(Op
.OP_NONE
)
953 comb
+= req_op
.eq(op
)
954 comb
+= req_go
.eq(go
)
956 # Version of the row number that is valid one cycle earlier
957 # in the cases where we need to read the cache data BRAM.
958 # If we're stalling then we need to keep reading the last
960 # if r0_stall = '0' then
961 with m
.If(~r0_stall
):
962 # if m_in.valid = '1' then
963 with m
.If(m_in
.valid
):
964 # early_req_row <= get_row(m_in.addr);
965 comb
+= early_req_row
.eq(get_row(m_in
.addr
))
968 # early_req_row <= get_row(d_in.addr);
969 comb
+= early_req_row
.eq(get_row(d_in
.addr
))
973 # early_req_row <= req_row;
974 comb
+= early_req_row
.eq(req_row
)
978 # Handle load-with-reservation and store-conditional instructions
979 def reservation_comb(self
, cancel_store
, set_rsrv
, clear_rsrv
,
980 r0_valid
, r0
, reservation
):
986 # cancel_store <= '0';
989 # if r0_valid = '1' and r0.req.reserve = '1' then
990 with m
.If(r0_valid
& r0
.req
.reserve
):
992 # -- XXX generate alignment interrupt if address
993 # -- is not aligned XXX or if r0.req.nc = '1'
994 # if r0.req.load = '1' then
995 # XXX generate alignment interrupt if address
996 # is not aligned XXX or if r0.req.nc = '1'
997 with m
.If(r0
.req
.load
):
998 # -- load with reservation
1000 # load with reservation
1004 # -- store conditional
1005 # clear_rsrv <= '1';
1007 comb
+= clear_rsrv
.eq(1)
1008 # if reservation.valid = '0' or r0.req.addr(63
1009 # downto LINE_OFF_BITS) /= reservation.addr then
1010 with m
.If(~reservation
.valid
1011 | r0
.req
.addr
[LINE_OFF_BITS
:64]):
1012 # cancel_store <= '1';
1013 comb
+= cancel_store
.eq(1)
1019 def reservation_reg(self
, r0_valid
, access_ok
, clear_rsrv
,
1026 # if rising_edge(clk) then
1028 # reservation.valid <= '0';
1029 # TODO understand how resets work in nmigen
1030 # elsif r0_valid = '1' and access_ok = '1' then
1031 with m
.Elif(r0_valid
& access_ok
)""
1032 # if clear_rsrv = '1' then
1033 with m
.If(clear_rsrv
):
1034 # reservation.valid <= '0';
1035 sync
+= reservation
.valid
.ea(0)
1036 # elsif set_rsrv = '1' then
1037 with m
.Elif(set_rsrv
):
1038 # reservation.valid <= '1';
1039 # reservation.addr <=
1040 # r0.req.addr(63 downto LINE_OFF_BITS);
1041 sync
+= reservation
.valid
.eq(1)
1042 sync
+= reservation
.addr
.eq(
1043 r0
.req
.addr
[LINE_OFF_BITS
:64]
1050 # Return data for loads & completion control logic
1051 def writeback_control(self
, r1
, cache_out
, d_out
, m_out
):
1056 # variable data_out : std_ulogic_vector(63 downto 0);
1057 # variable data_fwd : std_ulogic_vector(63 downto 0);
1058 # variable j : integer;
1059 data_out
= Signal(64)
1060 data_fwd
= Signal(64)
1064 # -- Use the bypass if are reading the row that was
1065 # -- written 1 or 2 cycles ago, including for the
1066 # -- slow_valid = 1 case (i.e. completing a load
1067 # -- miss or a non-cacheable load).
1068 # if r1.use_forward1 = '1' then
1069 # Use the bypass if are reading the row that was
1070 # written 1 or 2 cycles ago, including for the
1071 # slow_valid = 1 case (i.e. completing a load
1072 # miss or a non-cacheable load).
1073 with m
.If(r1
.use_forward1
):
1074 # data_fwd := r1.forward_data1;
1075 comb
+= data_fwd
.eq(r1
.forward_data1
)
1078 # data_fwd := r1.forward_data2;
1079 comb
+= data_fwd
.eq(r1
.forward_data2
)
1082 # data_out := cache_out(r1.hit_way);
1083 comb
+= data_out
.eq(cache_out
[r1
.hit_way
])
1085 # for i in 0 to 7 loop
1090 # if r1.forward_sel(i) = '1' then
1091 with m
.If(r1
.forward_sel
[i
]):
1092 # data_out(j + 7 downto j) := data_fwd(j + 7 downto j);
1093 comb
+= data_out
[j
:j
+8].eq(data_fwd
[j
:j
+8])
1097 # d_out.valid <= r1.ls_valid;
1098 # d_out.data <= data_out;
1099 # d_out.store_done <= not r1.stcx_fail;
1100 # d_out.error <= r1.ls_error;
1101 # d_out.cache_paradox <= r1.cache_paradox;
1102 comb
+= d_out
.valid
.eq(r1
.ls_valid
)
1103 comb
+= d_out
.data
.eq(data_out
)
1104 comb
+= d_out
.store_done
.eq(~r1
.stcx_fail
)
1105 comb
+= d_out
.error
.eq(r1
.ls_error
)
1106 comb
+= d_out
.cache_paradox
.eq(r1
.cache_paradox
)
1109 # m_out.done <= r1.mmu_done;
1110 # m_out.err <= r1.mmu_error;
1111 # m_out.data <= data_out;
1112 comb
+= m_out
.done
.eq(r1
.mmu_done
)
1113 comb
+= m_out
.err
.eq(r1
.mmu_error
)
1114 comb
+= m_out
.data
.eq(data_out
)
1116 # -- We have a valid load or store hit or we just completed
1117 # -- a slow op such as a load miss, a NC load or a store
1119 # -- Note: the load hit is delayed by one cycle. However it
1120 # -- can still not collide with r.slow_valid (well unless I
1121 # -- miscalculated) because slow_valid can only be set on a
1122 # -- subsequent request and not on its first cycle (the state
1123 # -- machine must have advanced), which makes slow_valid
1124 # -- at least 2 cycles from the previous hit_load_valid.
1126 # -- Sanity: Only one of these must be set in any given cycle
1127 # assert (r1.slow_valid and r1.stcx_fail) /= '1'
1128 # report "unexpected slow_valid collision with stcx_fail"
1130 # assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid)
1131 # /= '1' report "unexpected hit_load_delayed collision with
1132 # slow_valid" severity FAILURE;
1133 # We have a valid load or store hit or we just completed
1134 # a slow op such as a load miss, a NC load or a store
1136 # Note: the load hit is delayed by one cycle. However it
1137 # can still not collide with r.slow_valid (well unless I
1138 # miscalculated) because slow_valid can only be set on a
1139 # subsequent request and not on its first cycle (the state
1140 # machine must have advanced), which makes slow_valid
1141 # at least 2 cycles from the previous hit_load_valid.
1143 # Sanity: Only one of these must be set in any given cycle
1144 assert (r1
.slow_valid
& r1
.stcx_fail
) != 1 "unexpected" \
1145 "slow_valid collision with stcx_fail -!- severity FAILURE"
1147 assert ((r1
.slow_valid | r1
.stcx_fail
) | r1
.hit_load_valid
) != 1
1148 "unexpected hit_load_delayed collision with slow_valid -!-" \
1151 # if r1.mmu_req = '0' then
1152 with m
.If(~r1
._mmu_req
):
1153 # -- Request came from loadstore1...
1154 # -- Load hit case is the standard path
1155 # if r1.hit_load_valid = '1' then
1156 # Request came from loadstore1...
1157 # Load hit case is the standard path
1158 with m
.If(r1
.hit_load_valid
):
1160 # "completing load hit data=" & to_hstring(data_out);
1161 print(f
"completing load hit data={data_out}")
1164 # -- error cases complete without stalling
1165 # if r1.ls_error = '1' then
1166 # error cases complete without stalling
1167 with m
.If(r1
.ls_error
):
1168 # report "completing ld/st with error";
1169 print("completing ld/st with error")
1172 # -- Slow ops (load miss, NC, stores)
1173 # if r1.slow_valid = '1' then
1174 # Slow ops (load miss, NC, stores)
1175 with m
.If(r1
.slow_valid
):
1177 # "completing store or load miss data="
1178 # & to_hstring(data_out);
1179 print(f
"completing store or load miss data={data_out}")
1184 # -- Request came from MMU
1185 # if r1.hit_load_valid = '1' then
1186 # Request came from MMU
1187 with m
.If(r1
.hit_load_valid
):
1188 # report "completing load hit to MMU, data="
1189 # & to_hstring(m_out.data);
1190 print(f
"completing load hit to MMU, data={m_out.data}")
1193 # -- error cases complete without stalling
1194 # if r1.mmu_error = '1' then
1195 # report "completing MMU ld with error";
1196 # error cases complete without stalling
1197 with m
.If(r1
.mmu_error
):
1198 print("combpleting MMU ld with error")
1201 # -- Slow ops (i.e. load miss)
1202 # if r1.slow_valid = '1' then
1203 # Slow ops (i.e. load miss)
1204 with m
.If(r1
.slow_valid
):
1205 # report "completing MMU load miss, data="
1206 # & to_hstring(m_out.data);
1207 print("completing MMU load miss, data={m_out.data}")
1213 # -- Generate a cache RAM for each way. This handles the normal
1214 # -- reads, writes from reloads and the special store-hit update
1217 # -- Note: the BRAMs have an extra read buffer, meaning the output
1218 # -- is pipelined an extra cycle. This differs from the
1219 # -- icache. The writeback logic needs to take that into
1220 # -- account by using 1-cycle delayed signals for load hits.
1222 # rams: for i in 0 to NUM_WAYS-1 generate
1223 # signal do_read : std_ulogic;
1224 # signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1225 # signal do_write : std_ulogic;
1226 # signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1228 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
1229 # signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
1230 # signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
1231 # signal dout : cache_row_t;
1233 # way: entity work.cache_ram
1235 # ROW_BITS => ROW_BITS,
1236 # WIDTH => wishbone_data_bits,
1242 # rd_addr => rd_addr,
1244 # wr_sel => wr_sel_m,
1245 # wr_addr => wr_addr,
1246 # wr_data => wr_data
1250 class TODO(Elaboratable
):
1254 def elaborate(self
, platform
):
1261 # -- Cache hit reads
1264 # std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
1265 # cache_out(i) <= dout;
1267 comb
+= do_read
.eq(1)
1268 comb
+= rd_addr
.eq(Signal(ROW
))
1269 comb
+= cache_out
[i
].eq(dout
)
1273 # -- Defaults to wishbone read responses (cache refill)
1275 # -- For timing, the mux on wr_data/sel/addr is not
1276 # -- dependent on anything other than the current state.
1279 # Defaults to wishbone read responses (cache refill)
1281 # For timing, the mux on wr_data/sel/addr is not
1282 # dependent on anything other than the current state.
1283 # wr_sel_m <= (others => '0');
1284 comb
+= wr_sel_m
.eq(0)
1287 comb
+= do_write
.eq(0)
1288 # if r1.write_bram = '1' then
1289 with m
.If(r1
.write_bram
):
1290 # -- Write store data to BRAM. This happens one
1291 # -- cycle after the store is in r0.
1292 # Write store data to BRAM. This happens one
1293 # cycle after the store is in r0.
1294 # wr_data <= r1.req.data;
1295 # wr_sel <= r1.req.byte_sel;
1296 # wr_addr <= std_ulogic_vector(to_unsigned(
1297 # get_row(r1.req.real_addr), ROW_BITS
1299 comb
+= wr_data
.eq(r1
.req
.data
)
1300 comb
+= wr_sel
.eq(r1
.req
.byte_sel
)
1301 comb
+= wr_addr
.eq(Signal(get_row(r1
.req
.real_addr
)))
1303 # if i = r1.req.hit_way then
1304 with m
.If(i
== r1
.req
.hit_way
):
1306 comb
+= do_write
.eq(1)
1310 # -- Otherwise, we might be doing a reload or a DCBZ
1311 # if r1.dcbz = '1' then
1312 # Otherwise, we might be doing a reload or a DCBZ
1314 # wr_data <= (others => '0');
1315 comb
+= wr_data
.eq(0)
1318 # wr_data <= wishbone_in.dat;
1319 comb
+= wr_data
.eq(wishbone_in
.dat
)
1322 # wr_addr <= std_ulogic_vector(to_unsigned(
1323 # r1.store_row, ROW_BITS
1325 # wr_sel <= (others => '1');
1326 comb
+= wr_addr
.eq(Signal(r1
.store_row
))
1327 comb
+= wr_sel
.eq(1)
1329 # if r1.state = RELOAD_WAIT_ACK and
1330 # wishbone_in.ack = '1' and replace_way = i then
1331 with m
.If(r1
.state
== State
.RELOAD_WAIT_ACK
1332 & wishbone_in
.ack
& relpace_way
== i
):
1334 comb
+= do_write
.eq(1)
1338 # -- Mask write selects with do_write since BRAM
1339 # -- doesn't have a global write-enable
1340 # if do_write = '1' then
1341 # -- Mask write selects with do_write since BRAM
1342 # -- doesn't have a global write-enable
1343 with m
.If(do_write
):
1344 # wr_sel_m <= wr_sel;
1345 comb
+= wr_sel_m
.eq(wr_sel
)
1350 # Cache hit synchronous machine for the easy case.
1351 # This handles load hits.
1352 # It also handles error cases (TLB miss, cache paradox)
1353 def dcache_fast_hit(self
, req_op
, r0_valid
, r1
, ):
1359 # if rising_edge(clk) then
1360 # if req_op /= OP_NONE then
1361 with m
.If(req_op
!= Op
.OP_NONE
):
1362 # report "op:" & op_t'image(req_op) &
1363 # " addr:" & to_hstring(r0.req.addr) &
1364 # " nc:" & std_ulogic'image(r0.req.nc) &
1365 # " idx:" & integer'image(req_index) &
1366 # " tag:" & to_hstring(req_tag) &
1367 # " way: " & integer'image(req_hit_way);
1368 print(f
"op:{req_op} addr:{r0.req.addr} nc: {r0.req.nc}" \
1369 f
"idx:{req_index} tag:{req_tag} way: {req_hit_way}"
1372 # if r0_valid = '1' then
1373 with m
.If(r0_valid
):
1374 # r1.mmu_req <= r0.mmu_req;
1375 sync
+= r1
.mmu_req
.eq(r0
.mmu_req
)
1378 # -- Fast path for load/store hits.
1379 # -- Set signals for the writeback controls.
1380 # r1.hit_way <= req_hit_way;
1381 # r1.hit_index <= req_index;
1382 # Fast path for load/store hits.
1383 # Set signals for the writeback controls.
1384 sync
+= r1
.hit_way
.eq(req_hit_way
)
1385 sync
+= r1
.hit_index
.eq(req_index
)
1387 # if req_op = OP_LOAD_HIT then
1388 with m
.If(req_op
== Op
.OP_LOAD_HIT
):
1389 # r1.hit_load_valid <= '1';
1390 sync
+= r1
.hit_load_valid
.eq(1)
1394 # r1.hit_load_valid <= '0';
1395 sync
+= r1
.hit_load_valid
.eq(0)
1398 # if req_op = OP_LOAD_HIT or req_op = OP_STORE_HIT then
1399 with m
.If(req_op
== Op
.OP_LOAD_HIT | req_op
== Op
.OP_STORE_HIT
):
1400 # r1.cache_hit <= '1';
1401 sync
+= r1
.cache_hit
.eq(1)
1404 # r1.cache_hit <= '0';
1405 sync
+= r1
.cache_hit
.eq(0)
1408 # if req_op = OP_BAD then
1409 with m
.If(req_op
== Op
.OP_BAD
):
1410 # report "Signalling ld/st error valid_ra=" &
1411 # std_ulogic'image(valid_ra) & " rc_ok=" &
1412 # std_ulogic'image(rc_ok) & " perm_ok=" &
1413 # std_ulogic'image(perm_ok);
1414 print(f
"Signalling ld/st error valid_ra={valid_ra}"
1415 f
"rc_ok={rc_ok} perm_ok={perm_ok}"
1417 # r1.ls_error <= not r0.mmu_req;
1418 # r1.mmu_error <= r0.mmu_req;
1419 # r1.cache_paradox <= access_ok;
1420 sync
+= r1
.ls_error
.eq(~r0
.mmu_req
)
1421 sync
+= r1
.mmu_error
.eq(r0
.mmu_req
)
1422 sync
+= r1
.cache_paradox
.eq(access_ok
)
1426 # r1.ls_error <= '0';
1427 # r1.mmu_error <= '0';
1428 # r1.cache_paradox <= '0';
1429 sync
+= r1
.ls_error
.eq(0)
1430 sync
+= r1
.mmu_error
.eq(0)
1431 sync
+= r1
.cache_paradox
.eq(0)
1434 # if req_op = OP_STCX_FAIL then
1435 with m
.If(req_op
== Op
.OP_STCX_FAIL
):
1436 # r1.stcx_fail <= '1';
1441 # r1.stcx_fail <= '0';
1442 sync
+= r1
.stcx_fail
.eq(0)
1445 # -- Record TLB hit information for updating TLB PLRU
1446 # r1.tlb_hit <= tlb_hit;
1447 # r1.tlb_hit_way <= tlb_hit_way;
1448 # r1.tlb_hit_index <= tlb_req_index;
1449 # Record TLB hit information for updating TLB PLRU
1450 sync
+= r1
.tlb_hit
.eq(tlb_hit
)
1451 sync
+= r1
.tlb_hit_way
.eq(tlb_hit_way
)
1452 sync
+= r1
.tlb_hit_index
.eq(tlb_req_index
)
1456 # Memory accesses are handled by this state machine:
1458 # * Cache load miss/reload (in conjunction with "rams")
1459 # * Load hits for non-cachable forms
1460 # * Stores (the collision case is handled in "rams")
1462 # All wishbone requests generation is done here.
1463 # This machine operates at stage 1.
1464 def dcache_slow(self
, r1
, use_forward1_next
, cache_valid_bits
, r0
,
1465 r0_valid
, req_op
, cache_tag
, req_go
, ra
, wb_in
):
1470 # variable stbs_done : boolean;
1471 # variable req : mem_access_request_t;
1472 # variable acks : unsigned(2 downto 0);
1473 stbs_done
= Signal()
1474 req
= MemAccessRequest()
1482 # if rising_edge(clk) then
1483 # r1.use_forward1 <= use_forward1_next;
1484 # r1.forward_sel <= (others => '0');
1485 sync
+= r1
.use_forward1
.eq(use_forward1_next
)
1486 sync
+= r1
.forward_sel
.eq(0)
1488 # if use_forward1_next = '1' then
1489 with m
.If(use_forward1_next
):
1490 # r1.forward_sel <= r1.req.byte_sel;
1491 sync
+= r1
.forward_sel
.eq(r1
.req
.byte_sel
)
1493 # elsif use_forward2_next = '1' then
1494 with m
.Elif(use_forward2_next
):
1495 # r1.forward_sel <= r1.forward_sel1;
1496 sync
+= r1
.forward_sel
.eq(r1
.forward_sel1
)
1499 # r1.forward_data2 <= r1.forward_data1;
1500 sync
+= r1
.forward_data2
.eq(r1
.forward_data1
)
1502 # if r1.write_bram = '1' then
1503 with m
.If(r1
.write_bram
):
1504 # r1.forward_data1 <= r1.req.data;
1505 # r1.forward_sel1 <= r1.req.byte_sel;
1506 # r1.forward_way1 <= r1.req.hit_way;
1507 # r1.forward_row1 <= get_row(r1.req.real_addr);
1508 # r1.forward_valid1 <= '1';
1509 sync
+= r1
.forward_data1
.eq(r1
.req
.data
)
1510 sync
+= r1
.forward_sel1
.eq(r1
.req
.byte_sel
)
1511 sync
+= r1
.forward_way1
.eq(r1
.req
.hit_way
)
1512 sync
+= r1
.forward_row1
.eq(get_row(r1
.req
.real_addr
))
1513 sync
+= r1
.forward_valid1
.eq(1)
1517 # if r1.dcbz = '1' then
1519 # r1.forward_data1 <= (others => '0');
1520 sync
+= r1
.forward_data1
.eq(0)
1524 # r1.forward_data1 <= wishbone_in.dat;
1525 sync
+= r1
.forward_data1
.eq(wb_in
.dat
)
1528 # r1.forward_sel1 <= (others => '1');
1529 # r1.forward_way1 <= replace_way;
1530 # r1.forward_row1 <= r1.store_row;
1531 # r1.forward_valid1 <= '0';
1532 sync
+= r1
.forward_sel1
.eq(1)
1533 sync
+= r1
.forward_way1
.eq(replace_way
)
1534 sync
+= r1
.forward_row1
.eq(r1
.store_row
)
1535 sync
+= r1
.forward_valid1
.eq(0)
1538 # -- On reset, clear all valid bits to force misses
1540 # On reset, clear all valid bits to force misses
1541 # TODO figure out how reset signal works in nmigeni
1542 with m
.If("""TODO RST???"""):
1543 # for i in index_t loop
1544 for i
in range(INDEX
):
1545 # cache_valids(i) <= (others => '0');
1546 sync
+= cache_valid_bits
[i
].eq(0)
1551 # r1.slow_valid <= '0';
1554 # r1.ls_valid <= '0';
1555 # r1.mmu_done <= '0';
1556 sync
+= r1
.state
.eq(State
.IDLE
)
1557 sync
+= r1
.full
.eq(0)
1558 sync
+= r1
.slow_valid
.eq(0)
1559 sync
+= r1
.wb
.cyc
.eq(0)
1560 sync
+= r1
.wb
.stb
.eq(0)
1561 sync
+= r1
.ls_valid
.eq(0)
1562 sync
+= r1
.mmu_done
.eq(0)
1564 # -- Not useful normally but helps avoiding
1565 # -- tons of sim warnings
1566 # Not useful normally but helps avoiding
1567 # tons of sim warnings
1568 # r1.wb.adr <= (others => '0');
1569 sync
+= r1
.wb
.adr
.eq(0)
1572 # -- One cycle pulses reset
1573 # r1.slow_valid <= '0';
1574 # r1.write_bram <= '0';
1575 # r1.inc_acks <= '0';
1576 # r1.dec_acks <= '0';
1578 # r1.ls_valid <= '0';
1579 # -- complete tlbies and TLB loads in the third cycle
1580 # r1.mmu_done <= r0_valid and (r0.tlbie or r0.tlbld);
1581 # One cycle pulses reset
1582 sync
+= r1
.slow_valid
.eq(0)
1583 sync
+= r1
.write_bram
.eq(0)
1584 sync
+= r1
.inc_acks
.eq(0)
1585 sync
+= r1
.dec_acks
.eq(0)
1587 sync
+= r1
.ls_valid
.eq(0)
1588 # complete tlbies and TLB loads in the third cycle
1589 sync
+= r1
.mmu_done
.eq(r0_valid
& (r0
.tlbie | r0
.tlbld
))
1591 # if req_op = OP_LOAD_HIT or req_op = OP_STCX_FAIL then
1592 with m
.If(req_op
== Op
.OP_LOAD_HIT
1593 | req_op
== Op
.OP_STCX_FAIL
):
1594 # if r0.mmu_req = '0' then
1595 with m
.If(~r0
.mmu_req
):
1596 # r1.ls_valid <= '1';
1597 sync
+= r1
.ls_valid
.eq(1)
1600 # r1.mmu_done <= '1';
1601 sync
+= r1
.mmu_done
.eq(1)
1605 # if r1.write_tag = '1' then
1606 with m
.If(r1
.write_tag
):
1607 # -- Store new tag in selected way
1608 # for i in 0 to NUM_WAYS-1 loop
1609 # Store new tag in selected way
1610 for i
in range(NUM_WAYS
):
1611 # if i = replace_way then
1612 with m
.If(i
== replace_way
):
1613 # cache_tags(r1.store_index)(
1614 # (i + 1) * TAG_WIDTH - 1
1615 # downto i * TAG_WIDTH
1617 # (TAG_WIDTH - 1 downto TAG_BITS => '0')
1621 ][i
* TAG_WIDTH
:(i
+1) * TAG_WIDTH
].eq(
1622 Const(TAG_WIDTH
, TAG_WIDTH
)
1627 # r1.store_way <= replace_way;
1628 # r1.write_tag <= '0';
1629 sync
+= r1
.store_way
.eq(replace_way
)
1630 sync
+= r1
.write_tag
.eq(0)
1633 # -- Take request from r1.req if there is one there,
1634 # -- else from req_op, ra, etc.
1635 # if r1.full = '1' then
1636 # Take request from r1.req if there is one there,
1637 # else from req_op, ra, etc.
1640 sync
+= req
.eq(r1
.req
)
1645 # req.valid := req_go;
1646 # req.mmu_req := r0.mmu_req;
1647 # req.dcbz := r0.req.dcbz;
1648 # req.real_addr := ra;
1649 sync
+= req
.op
.eq(req_op
)
1650 sync
+= req
.valid
.eq(req_go
)
1651 sync
+= req
.mmu_req
.eq(r0
.mmu_req
)
1652 sync
+= req
.dcbz
.eq(r0
.req
.dcbz
)
1653 sync
+= req
.real_addr
.eq(ra
)
1655 # -- Force data to 0 for dcbz
1656 # if r0.req.dcbz = '0' then
1657 with m
.If(~r0
.req
.dcbz
):
1658 # req.data := r0.req.data;
1659 sync
+= req
.data
.eq(r0
.req
.data
)
1663 # req.data := (others => '0');
1664 sync
+= req
.data
.eq(0)
1667 # -- Select all bytes for dcbz
1668 # -- and for cacheable loads
1669 # if r0.req.dcbz = '1'
1670 # or (r0.req.load = '1' and r0.req.nc = '0') then
1671 # Select all bytes for dcbz
1672 # and for cacheable loads
1673 with m
.If(r0
.req
.dcbz |
(r0
.req
.load
& ~r0
.req
.nc
):
1674 # req.byte_sel := (others => '1');
1675 sync
+= req
.byte_sel
.eq(1)
1679 # req.byte_sel := r0.req.byte_sel;
1680 sync
+= req
.byte_sel
.eq(r0
.req
.byte_sel
)
1683 # req.hit_way := req_hit_way;
1684 # req.same_tag := req_same_tag;
1685 sync
+= req
.hit_way
.eq(req_hit_way
)
1686 sync
+= req
.same_tag
.eq(req_same_tag
)
1688 # -- Store the incoming request from r0,
1689 # -- if it is a slow request
1690 # -- Note that r1.full = 1 implies req_op = OP_NONE
1691 # if req_op = OP_LOAD_MISS or req_op = OP_LOAD_NC
1692 # or req_op = OP_STORE_MISS
1693 # or req_op = OP_STORE_HIT then
1694 # Store the incoming request from r0,
1695 # if it is a slow request
1696 # Note that r1.full = 1 implies req_op = OP_NONE
1697 with m
.If(req_op
== Op
.OP_LOAD_MISS
1698 | req_op
== Op
.OP_LOAD_NC
1699 | req_op
== Op
.OP_STORE_MISS
1700 | req_op
== Op
.OP_STORE_HIT
):
1704 sync
+= r1
.full
.eq(1)
1708 # -- Main state machine
1710 # Main state machine
1711 with m
.Switch(r1
.state
):
1714 with m
.Case(State
.IDLE
)
1715 # r1.wb.adr <= req.real_addr(
1716 # r1.wb.adr'left downto 0
1718 # r1.wb.sel <= req.byte_sel;
1719 # r1.wb.dat <= req.data;
1720 # r1.dcbz <= req.dcbz;
1722 # -- Keep track of our index and way
1723 # -- for subsequent stores.
1724 # r1.store_index <= get_index(req.real_addr);
1725 # r1.store_row <= get_row(req.real_addr);
1727 # get_row_of_line(get_row(req.real_addr)) - 1;
1728 # r1.reload_tag <= get_tag(req.real_addr);
1729 # r1.req.same_tag <= '1';
1730 sync
+= r1
.wb
.adr
.eq(req
.real_addr
[0:r1
.wb
.adr
])
1731 sync
+= r1
.wb
.sel
.eq(req
.byte_sel
)
1732 sync
+= r1
.wb
.dat
.eq(req
.data
)
1733 sync
+= r1
.dcbz
.eq(req
.dcbz
)
1735 # Keep track of our index and way
1736 # for subsequent stores.
1737 sync
+= r1
.store_index
.eq(get_index(req
.real_addr
))
1738 sync
+= r1
.store_row
.eq(get_row(req
.real_addr
))
1739 sync
+= r1
.end_row_ix
.eq(
1740 get_row_of_line(get_row(req
.real_addr
))
1742 sync
+= r1
.reload_tag
.eq(get_tag(req
.real_addr
))
1743 sync
+= r1
.req
.same_tag
.eq(1)
1745 # if req.op = OP_STORE_HIT theni
1746 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
1747 # r1.store_way <= req.hit_way;
1748 sync
+= r1
.store_way
.eq(req
.hit_way
)
1751 # -- Reset per-row valid bits,
1752 # -- ready for handling OP_LOAD_MISS
1753 # for i in 0 to ROW_PER_LINE - 1 loop
1754 # Reset per-row valid bits,
1755 # ready for handling OP_LOAD_MISS
1756 for i
in range(ROW_PER_LINE
):
1757 # r1.rows_valid(i) <= '0';
1758 sync
+= r1
.rows_valid
[i
].eq(0)
1762 with m
.Switch(req
.op
):
1763 # when OP_LOAD_HIT =>
1764 with m
.Case(Op
.OP_LOAD_HIT
):
1765 # -- stay in IDLE state
1766 # stay in IDLE state
1769 # when OP_LOAD_MISS =>
1770 with m
.Case(Op
.OP_LOAD_MISS
):
1771 # -- Normal load cache miss,
1772 # -- start the reload machine
1773 # report "cache miss real addr:" &
1774 # to_hstring(req.real_addr) & " idx:" &
1775 # integer'image(get_index(req.real_addr)) &
1776 # " tag:" & to_hstring(get_tag(req.real_addr));
1777 # Normal load cache miss,
1778 # start the reload machine
1779 print(f
"cache miss real addr:" \
1780 f
"{req_real_addr}" \
1781 f
" idx:{get_index(req_real_addr)}" \
1782 f
" tag:{get_tag(req.real_addr)}")
1784 # -- Start the wishbone cycle
1788 # Start the wishbone cycle
1789 sync
+= r1
.wb
.we
.eq(0)
1790 sync
+= r1
.wb
.cyc
.eq(1)
1791 sync
+= r1
.wb
.stb
.eq(1)
1793 # -- Track that we had one request sent
1794 # r1.state <= RELOAD_WAIT_ACK;
1795 # r1.write_tag <= '1';
1796 # Track that we had one request sent
1797 sync
+= r1
.state
.eq(State
.RELOAD_WAIT_ACK
)
1798 sync
+= r1
.write_tag
.eq(1)
1800 # when OP_LOAD_NC =>
1801 with m
.Case(Op
.OP_LOAD_NC
):
1805 # r1.state <= NC_LOAD_WAIT_ACK;
1806 sync
+= r1
.wb
.cyc
.eq(1)
1807 sync
+= r1
.wb
.stb
.eq(1)
1808 sync
+= r1
.wb
.we
.eq(0)
1809 sync
+= r1
.state
.eq(State
.NC_LOAD_WAIT_ACK
)
1811 # when OP_STORE_HIT | OP_STORE_MISS =>
1812 with m
.Case(Op
.OP_STORE_HIT
1813 | Op
.OP_STORE_MISS
):
1814 # if req.dcbz = '0' then
1815 with m
.If(~req
.bcbz
):
1816 # r1.state <= STORE_WAIT_ACK;
1817 # r1.acks_pending <= to_unsigned(1, 3);
1819 # r1.slow_valid <= '1';
1820 sync
+= r1
.state
.eq(
1821 State
.STORE_WAIT_ACK
1823 sync
+= r1
.acks_pending
.eq(
1824 '''TODO to_unsignes(1,3)'''
1826 sync
+= r1
.full
.eq(0)
1827 sync
+= r1
.slow_valid
.eq(1)
1829 # if req.mmu_req = '0' then
1830 with m
.If(~req
.mmu_req
):
1831 # r1.ls_valid <= '1';
1832 sync
+= r1
.ls_valid
.eq(1)
1835 # r1.mmu_done <= '1';
1836 sync
+= r1
.mmu_done
.eq(1)
1839 # if req.op = OP_STORE_HIT then
1840 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
1841 # r1.write_bram <= '1';
1842 sync
+= r1
.write_bram
.eq(1)
1847 # -- dcbz is handled much like a load
1848 # -- miss except that we are writing
1849 # -- to memory instead of reading
1850 # r1.state <= RELOAD_WAIT_ACK;
1851 # dcbz is handled much like a load
1852 # miss except that we are writing
1853 # to memory instead of reading
1854 sync
+= r1
.state
.eq(Op
.RELOAD_WAIT_ACK
)
1856 # if req.op = OP_STORE_MISS then
1857 with m
.If(req
.op
== Op
.OP_STORE_MISS
):
1858 # r1.write_tag <= '1';
1859 sync
+= r1
.write_tag
.eq(1)
1866 sync
+= r1
.wb
.we
.eq(1)
1867 sync
+= r1
.wb
.cyc
.eq(1)
1868 sync
+= r1
.wb
.stb
.eq(1)
1870 # -- OP_NONE and OP_BAD do nothing
1871 # -- OP_BAD & OP_STCX_FAIL were handled above already
1874 # when OP_STCX_FAIL =>
1875 # OP_NONE and OP_BAD do nothing
1876 # OP_BAD & OP_STCX_FAIL were
1877 # handled above already
1878 with m
.Case(Op
.OP_NONE
):
1881 with m
.Case(OP_BAD
):
1884 with m
.Case(OP_STCX_FAIL
):
1888 # when RELOAD_WAIT_ACK =>
1889 with m
.Case(State
.RELOAD_WAIT_ACK
):
1890 # -- Requests are all sent if stb is 0
1891 # Requests are all sent if stb is 0
1892 sync
+= stbs_done
.eq(~r1
.wb
.stb
)
1893 # stbs_done := r1.wb.stb = '0';
1895 # -- If we are still sending requests,
1896 # -- was one accepted?
1897 # if wishbone_in.stall = '0' and not stbs_done then
1898 # If we are still sending requests,
1900 with m
.If(~wb_in
.stall
& ~stbs_done
):
1901 # -- That was the last word ? We are done sending.
1902 # -- Clear stb and set stbs_done so we can handle
1903 # -- an eventual last ack on the same cycle.
1904 # if is_last_row_addr(
1905 # r1.wb.adr, r1.end_row_ix
1907 # That was the last word?
1908 # We are done sending.
1909 # Clear stb and set stbs_done
1910 # so we can handle an eventual
1911 # last ack on the same cycle.
1912 with m
.If(is_last_row_addr(
1913 r1
.wb
.adr
, r1
.end_row_ix
)):
1915 # stbs_done := true;
1916 sync
+= r1
.wb
.stb
.eq(0)
1917 sync
+= stbs_done
.eq(0)
1920 # -- Calculate the next row address
1921 # r1.wb.adr <= next_row_addr(r1.wb.adr);
1922 # Calculate the next row address
1923 sync
+= r1
.wb
.adr
.eq(next_row_addr(r1
.wb
.adr
))
1926 # -- Incoming acks processing
1927 # r1.forward_valid1 <= wishbone_in.ack;
1928 # Incoming acks processing
1929 sync
+= r1
.forward_valid1
.eq(wb_in
.ack
)
1931 # if wishbone_in.ack = '1' then
1932 with m
.If(wb_in
.ack
):
1934 # r1.store_row mod ROW_PER_LINE
1936 sync
+= r1
.rows_valid
[
1937 r1
.store_row
% ROW_PER_LINE
1940 # -- If this is the data we were looking for,
1941 # -- we can complete the request next cycle.
1942 # -- Compare the whole address in case the
1943 # -- request in r1.req is not the one that
1944 # -- started this refill.
1945 # if r1.full = '1' and r1.req.same_tag = '1'
1946 # and ((r1.dcbz = '1' and r1.req.dcbz = '1')
1947 # or (r1.dcbz = '0' and r1.req.op = OP_LOAD_MISS))
1948 # and r1.store_row = get_row(r1.req.real_addr) then
1949 # If this is the data we were looking for,
1950 # we can complete the request next cycle.
1951 # Compare the whole address in case the
1952 # request in r1.req is not the one that
1953 # started this refill.
1954 with m
.If(r1
.full
& r1
.req
.same_tag
&
1955 ((r1
.dcbz
& r1
.req
.dcbz
)
1957 r1
.req
.op
== Op
.OP_LOAD_MISS
)
1960 == get_row(r1
.req
.real_addr
):
1962 # r1.slow_valid <= '1';
1963 sync
+= r1
.full
.eq(0)
1964 sync
+= r1
.slow_valid
.eq(1)
1966 # if r1.mmu_req = '0' then
1967 with m
.If(~r1
.mmu_req
):
1968 # r1.ls_valid <= '1';
1969 sync
+= r1
.ls_valid
.eq(1)
1972 # r1.mmu_done <= '1';
1973 sync
+= r1
.mmu_done
.eq(1)
1975 # r1.forward_sel <= (others => '1');
1976 # r1.use_forward1 <= '1';
1977 sync
+= r1
.forward_sel
.eq(1)
1978 sync
+= r1
.use_forward1
.eq(1)
1981 # -- Check for completion
1982 # if stbs_done and is_last_row(r1.store_row,
1983 # r1.end_row_ix) then
1984 # Check for completion
1985 with m
.If(stbs_done
&
1986 is_last_row(r1
.store_row
,
1989 # -- Complete wishbone cycle
1991 # Complete wishbone cycle
1992 sync
+= r1
.wb
.cyc
.eq(0)
1994 # -- Cache line is now valid
1995 # cache_valids(r1.store_index)(
1998 # Cache line is now valid
1999 sync
+= cache_valid_bits
[
2001 ][r1
.store_way
].eq(1)
2004 sync
+= r1
.state
.eq(State
.IDLE
)
2007 # -- Increment store row counter
2008 # r1.store_row <= next_row(r1.store_row);
2009 # Increment store row counter
2010 sync
+= r1
.store_row
.eq(next_row(
2015 # when STORE_WAIT_ACK =>
2016 with m
.Case(State
.STORE_WAIT_ACK
):
2017 # stbs_done := r1.wb.stb = '0';
2018 # acks := r1.acks_pending;
2019 sync
+= stbs_done
.eq(~r1
.wb
.stb
)
2020 sync
+= acks
.eq(r1
.acks_pending
)
2022 # if r1.inc_acks /= r1.dec_acks then
2023 with m
.If(r1
.inc_acks
!= r1
.dec_acks
):
2025 # if r1.inc_acks = '1' then
2026 with m
.If(r1
.inc_acks
):
2028 sync
+= acks
.eq(acks
+ 1)
2033 sync
+= acks
.eq(acks
- 1)
2037 # r1.acks_pending <= acks;
2038 sync
+= r1
.acks_pending
.eq(acks
)
2040 # -- Clear stb when slave accepted request
2041 # if wishbone_in.stall = '0' then
2042 # Clear stb when slave accepted request
2043 with m
.If(~wb_in
.stall
):
2044 # -- See if there is another store waiting
2045 # -- to be done which is in the same real page.
2046 # if req.valid = '1' then
2047 # See if there is another store waiting
2048 # to be done which is in the same real page.
2049 with m
.If(req
.valid
):
2051 # SET_SIZE_BITS - 1 downto 0
2052 # ) <= req.real_addr(
2053 # SET_SIZE_BITS - 1 downto 0
2055 # r1.wb.dat <= req.data;
2056 # r1.wb.sel <= req.byte_sel;
2057 sync
+= r1
.wb
.adr
[0:SET_SIZE_BITS
].eq(
2058 req
.real_addr
[0:SET_SIZE_BITS
]
2062 # if acks < 7 and req.same_tag = '1'
2063 # and (req.op = OP_STORE_MISS
2064 # or req.op = OP_STORE_HIT) then
2065 with m
.Elif(acks
< 7 & req
.same_tag
&
2066 (req
.op
== Op
.Op_STORE_MISS
2067 | req
.op
== Op
.OP_SOTRE_HIT
)):
2069 # stbs_done := false;
2070 sync
+= r1
.wb
.stb
.eq(1)
2071 sync
+= stbs_done
.eq(0)
2073 # if req.op = OP_STORE_HIT then
2074 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
2075 # r1.write_bram <= '1';
2076 sync
+= r1
.write_bram
.eq(1)
2079 # r1.slow_valid <= '1';
2080 sync
+= r1
.full
.eq(0)
2081 sync
+= r1
.slow_valid
.eq(1)
2083 # -- Store requests never come from the MMU
2084 # r1.ls_valid <= '1';
2085 # stbs_done := false;
2086 # r1.inc_acks <= '1';
2087 # Store request never come from the MMU
2088 sync
+= r1
.ls_valid
.eq(1)
2089 sync
+= stbs_done
.eq(0)
2090 sync
+= r1
.inc_acks
.eq(1)
2094 # stbs_done := true;
2095 sync
+= r1
.wb
.stb
.eq(0)
2096 sync
+= stbs_done
.eq(1)
2100 # -- Got ack ? See if complete.
2101 # if wishbone_in.ack = '1' then
2102 # Got ack ? See if complete.
2103 with m
.If(wb_in
.ack
):
2104 # if stbs_done and acks = 1 then
2105 with m
.If(stbs_done
& acks
)
2109 sync
+= r1
.state
.eq(State
.IDLE
)
2110 sync
+= r1
.wb
.cyc
.eq(0)
2111 sync
+= r1
.wb
.stb
.eq(0)
2113 # r1.dec_acks <= '1';
2114 sync
+= r1
.dec_acks
.eq(1)
2117 # when NC_LOAD_WAIT_ACK =>
2118 with m
.Case(State
.NC_LOAD_WAIT_ACK
):
2119 # -- Clear stb when slave accepted request
2120 # if wishbone_in.stall = '0' then
2121 # Clear stb when slave accepted request
2122 with m
.If(~wb_in
.stall
):
2124 sync
+= r1
.wb
.stb
.eq(0)
2127 # -- Got ack ? complete.
2128 # if wishbone_in.ack = '1' then
2129 # Got ack ? complete.
2130 with m
.If(wb_in
.ack
):
2133 # r1.slow_valid <= '1';
2134 sync
+= r1
.state
.eq(State
.IDLE
)
2135 sync
+= r1
.full
.eq(0)
2136 sync
+= r1
.slow_valid
.eq(1)
2138 # if r1.mmu_req = '0' then
2139 with m
.If(~r1
.mmu_req
):
2140 # r1.ls_valid <= '1';
2141 sync
+= r1
.ls_valid
.eq(1)
2145 # r1.mmu_done <= '1';
2146 sync
+= r1
.mmu_done
.eq(1)
2149 # r1.forward_sel <= (others => '1');
2150 # r1.use_forward1 <= '1';
2153 sync
+= r1
.forward_sel
.eq(1)
2154 sync
+= r1
.use_forward1
.eq(1)
2155 sync
+= r1
.wb
.cyc
.eq(0)
2156 sync
+= r1
.wb
.stb
.eq(0)
2163 # dc_log: if LOG_LENGTH > 0 generate
2164 # TODO learn how to tranlate vhdl generate into nmigen
2165 def dcache_log(self
, r1
, valid_ra
, tlb_hit_way
, stall_out
,
2166 d_out
, wb_in
, log_out
):
2171 # signal log_data : std_ulogic_vector(19 downto 0);
2172 log_data
= Signal(20)
2177 # dcache_log: process(clk)
2179 # if rising_edge(clk) then
2180 # log_data <= r1.wb.adr(5 downto 3) &
2181 # wishbone_in.stall &
2183 # r1.wb.stb & r1.wb.cyc &
2186 # std_ulogic_vector(
2187 # to_unsigned(op_t'pos(req_op), 3)) &
2189 # std_ulogic_vector(
2190 # to_unsigned(tlb_hit_way, 3)) &
2192 # std_ulogic_vector(
2193 # to_unsigned(state_t'pos(r1.state), 3));
2194 sync
+= log_data
.eq(Cat(
2195 Const(r1
.state
, 3), valid_ra
, Const(tlb_hit_way
, 3),
2196 stall_out
, Const(req_op
, 3), d_out
.valid
, d_out
.error
,
2197 r1
.wb
.cyc
, r1
.wb
.stb
, wb_in
.ack
, wb_in
.stall
,
2202 # log_out <= log_data;
2203 # TODO ??? I am very confused need help
2204 comb
+= log_out
.eq(log_data
)
2208 def elaborate(self
, platform
):
2209 LINE_SIZE
= self
.LINE_SIZE
2210 NUM_LINES
= self
.NUM_LINES
2211 NUM_WAYS
= self
.NUM_WAYS
2212 TLB_SET_SIZE
= self
.TLB_SET_SIZE
2213 TLB_NUM_WAYS
= self
.TLB_NUM_WAYS
2214 TLB_LG_PGSZ
= self
.TLB_LG_PGSZ
2215 LOG_LENGTH
= self
.LOG_LENGTH
2217 # BRAM organisation: We never access more than
2218 # -- wishbone_data_bits at a time so to save
2219 # -- resources we make the array only that wide, and
2220 # -- use consecutive indices for to make a cache "line"
2222 # -- ROW_SIZE is the width in bytes of the BRAM
2223 # -- (based on WB, so 64-bits)
2224 ROW_SIZE
= WB_DATA_BITS
/ 8;
2226 # ROW_PER_LINE is the number of row (wishbone
2227 # transactions) in a line
2228 ROW_PER_LINE
= LINE_SIZE
// ROW_SIZE
2230 # BRAM_ROWS is the number of rows in BRAM needed
2231 # to represent the full dcache
2232 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
2235 # Bit fields counts in the address
2237 # REAL_ADDR_BITS is the number of real address
2238 # bits that we store
2241 # ROW_BITS is the number of bits to select a row
2242 ROW_BITS
= log2_int(BRAM_ROWS
)
2244 # ROW_LINE_BITS is the number of bits to select
2245 # a row within a line
2246 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
2248 # LINE_OFF_BITS is the number of bits for
2249 # the offset in a cache line
2250 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
2252 # ROW_OFF_BITS is the number of bits for
2253 # the offset in a row
2254 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
2256 # INDEX_BITS is the number if bits to
2257 # select a cache line
2258 INDEX_BITS
= log2_int(NUM_LINES
)
2260 # SET_SIZE_BITS is the log base 2 of the set size
2261 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
2263 # TAG_BITS is the number of bits of
2264 # the tag part of the address
2265 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
2267 # TAG_WIDTH is the width in bits of each way of the tag RAM
2268 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
2270 # WAY_BITS is the number of bits to select a way
2271 WAY_BITS
= log2_int(NUM_WAYS
)
2273 # Example of layout for 32 lines of 64 bytes:
2275 # .. tag |index| line |
2277 # .. | |---| | ROW_LINE_BITS (3)
2278 # .. | |--- - --| LINE_OFF_BITS (6)
2279 # .. | |- --| ROW_OFF_BITS (3)
2280 # .. |----- ---| | ROW_BITS (8)
2281 # .. |-----| | INDEX_BITS (5)
2282 # .. --------| | TAG_BITS (45)
2285 # subtype row_t is integer range 0 to BRAM_ROWS-1;
2286 # subtype index_t is integer range 0 to NUM_LINES-1;
2287 """wherever way_t is used to make a Signal it must be substituted with
2288 log2_int(NUM_WAYS) i.e. WAY_BITS. this because whilst the *range*
2289 of the number is 0..NUM_WAYS it requires log2_int(NUM_WAYS) i.e.
2290 WAY_BITS of space to store it
2292 # subtype way_t is integer range 0 to NUM_WAYS-1;
2293 # subtype row_in_line_t is unsigned(ROW_LINE_BITS-1 downto 0);
2294 ROW
= BRAM_ROWS
# yyyeah not really necessary, delete
2295 INDEX
= NUM_LINES
# yyyeah not really necessary, delete
2296 WAY
= NUM_WAYS
# yyyeah not really necessary, delete
2297 ROW_IN_LINE
= ROW_LINE_BITS
# yyyeah not really necessary, delete
2299 # -- The cache data BRAM organized as described above for each way
2300 # subtype cache_row_t is
2301 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
2302 # The cache data BRAM organized as described above for each way
2303 CACHE_ROW
= WB_DATA_BITS
2305 # -- The cache tags LUTRAM has a row per set.
2306 # -- Vivado is a pain and will not handle a
2307 # -- clean (commented) definition of the cache
2308 # -- tags as a 3d memory. For now, work around
2309 # -- it by putting all the tags
2310 # subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
2311 # The cache tags LUTRAM has a row per set.
2312 # Vivado is a pain and will not handle a
2313 # clean (commented) definition of the cache
2314 # tags as a 3d memory. For now, work around
2315 # it by putting all the tags
2316 CACHE_TAG
= TAG_BITS
2318 # -- type cache_tags_set_t is array(way_t) of cache_tag_t;
2319 # -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
2320 # constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
2321 # subtype cache_tags_set_t is
2322 # std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
2323 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
2324 # type cache_tags_set_t is array(way_t) of cache_tag_t;
2325 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
2326 TAG_RAM_WIDTH
= TAG_WIDTH
* NUM_WAYS
2328 CACHE_TAG_SET
= TAG_RAM_WIDTH
2330 def CacheTagArray():
2331 return Array(CacheTagSet() for x
in range(INDEX
))
2333 # -- The cache valid bits
2334 # subtype cache_way_valids_t is
2335 # std_ulogic_vector(NUM_WAYS-1 downto 0);
2336 # type cache_valids_t is array(index_t) of cache_way_valids_t;
2337 # type row_per_line_valid_t is
2338 # array(0 to ROW_PER_LINE - 1) of std_ulogic;
2339 # The cache valid bits
2340 CACHE_WAY_VALID_BITS
= NUM_WAYS
2342 def CacheValidBitsArray():
2343 return Array(CacheWayValidBits() for x
in range(INDEX
))
2345 def RowPerLineValidArray():
2346 return Array(Signal() for x
in range(ROW_PER_LINE
))
2348 # -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
2349 # signal cache_tags : cache_tags_array_t;
2350 # signal cache_tag_set : cache_tags_set_t;
2351 # signal cache_valids : cache_valids_t;
2353 # attribute ram_style : string;
2354 # attribute ram_style of cache_tags : signal is "distributed";
2355 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
2356 cache_tags
= CacheTagArray()
2357 cache_tag_set
= Signal(CACHE_TAG_SET
)
2358 cache_valid_bits
= CacheValidBitsArray()
2360 # TODO attribute ram_style : string;
2361 # TODO attribute ram_style of cache_tags : signal is "distributed";
2364 # constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
2365 # constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
2366 # constant TLB_EA_TAG_BITS : natural :=
2367 # 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
2368 # constant TLB_TAG_WAY_BITS : natural :=
2369 # TLB_NUM_WAYS * TLB_EA_TAG_BITS;
2370 # constant TLB_PTE_BITS : natural := 64;
2371 # constant TLB_PTE_WAY_BITS : natural :=
2372 # TLB_NUM_WAYS * TLB_PTE_BITS;
2374 TLB_SET_BITS
= log2_int(TLB_SET_SIZE
)
2375 TLB_WAY_BITS
= log2_int(TLB_NUM_WAYS
)
2376 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_SET_BITS
)
2377 TLB_TAG_WAY_BITS
= TLB_NUM_WAYS
* TLB_EA_TAG_BITS
2379 TLB_PTE_WAY_BITS
= TLB_NUM_WAYS
* TLB_PTE_BITS
;
2381 # subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
2382 # subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
2383 # subtype tlb_way_valids_t is
2384 # std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
2385 # type tlb_valids_t is
2386 # array(tlb_index_t) of tlb_way_valids_t;
2387 # subtype tlb_tag_t is
2388 # std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
2389 # subtype tlb_way_tags_t is
2390 # std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
2391 # type tlb_tags_t is
2392 # array(tlb_index_t) of tlb_way_tags_t;
2393 # subtype tlb_pte_t is
2394 # std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
2395 # subtype tlb_way_ptes_t is
2396 # std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
2397 # type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
2398 # type hit_way_set_t is array(tlb_way_t) of way_t;
2399 TLB_WAY
= TLB_NUM_WAYS
2401 TLB_INDEX
= TLB_SET_SIZE
2403 TLB_WAY_VALID_BITS
= TLB_NUM_WAYS
2405 def TLBValidBitsArray():
2407 Signal(TLB_WAY_VALID_BITS
) for x
in range(TLB_SET_SIZE
)
2410 TLB_TAG
= TLB_EA_TAG_BITS
2412 TLB_WAY_TAGS
= TLB_TAG_WAY_BITS
2416 Signal(TLB_WAY_TAGS
) for x
in range (TLB_SET_SIZE
)
2419 TLB_PTE
= TLB_PTE_BITS
2421 TLB_WAY_PTES
= TLB_PTE_WAY_BITS
2425 Signal(TLB_WAY_PTES
) for x
in range(TLB_SET_SIZE
)
2429 return Array(Signal(NUM_WAYS
) for x
in range(TLB_NUM_WAYS
))
2431 # signal dtlb_valids : tlb_valids_t;
2432 # signal dtlb_tags : tlb_tags_t;
2433 # signal dtlb_ptes : tlb_ptes_t;
2435 """note: these are passed to nmigen.hdl.Memory as "attributes".
2436 don't know how, just that they are.
2438 # attribute ram_style of dtlb_tags : signal is "distributed";
2439 # attribute ram_style of dtlb_ptes : signal is "distributed";
2440 dtlb_valid_bits
= TLBValidBitsArray()
2441 dtlb_tags
= TLBTagsArray()
2442 dtlb_ptes
= TLBPtesArray()
2443 # TODO attribute ram_style of
2444 # dtlb_tags : signal is "distributed";
2445 # TODO attribute ram_style of
2446 # dtlb_ptes : signal is "distributed";
2448 # signal r0 : reg_stage_0_t;
2449 # signal r0_full : std_ulogic;
2453 # signal r1 : reg_stage_1_t;
2456 # signal reservation : reservation_t;
2457 reservation
= Reservation()
2459 # -- Async signals on incoming request
2460 # signal req_index : index_t;
2461 # signal req_row : row_t;
2462 # signal req_hit_way : way_t;
2463 # signal req_tag : cache_tag_t;
2464 # signal req_op : op_t;
2465 # signal req_data : std_ulogic_vector(63 downto 0);
2466 # signal req_same_tag : std_ulogic;
2467 # signal req_go : std_ulogic;
2468 # Async signals on incoming request
2469 req_index
= Signal(INDEX
)
2470 req_row
= Signal(ROW
)
2471 req_hit_way
= Signal(WAY_BITS
)
2472 req_tag
= Signal(CACHE_TAG
)
2474 req_data
= Signal(64)
2475 req_same_tag
= Signal()
2478 # signal early_req_row : row_t;
2480 # signal cancel_store : std_ulogic;
2481 # signal set_rsrv : std_ulogic;
2482 # signal clear_rsrv : std_ulogic;
2484 # signal r0_valid : std_ulogic;
2485 # signal r0_stall : std_ulogic;
2487 # signal use_forward1_next : std_ulogic;
2488 # signal use_forward2_next : std_ulogic;
2489 early_req_row
= Signal(ROW
)
2491 cancel_store
= Signal()
2493 clear_rsrv
= Signal()
2498 use_forward1_next
= Signal()
2499 use_forward2_next
= Signal()
2501 # -- Cache RAM interface
2502 # type cache_ram_out_t is array(way_t) of cache_row_t;
2503 # signal cache_out : cache_ram_out_t;
2504 # Cache RAM interface
2506 return Array(Signal(CACHE_ROW
) for x
in range(NUM_WAYS
))
2508 cache_out
= CacheRamOut()
2510 # -- PLRU output interface
2511 # type plru_out_t is array(index_t) of
2512 # std_ulogic_vector(WAY_BITS-1 downto 0);
2513 # signal plru_victim : plru_out_t;
2514 # signal replace_way : way_t;
2515 # PLRU output interface
2517 return Array(Signal(WAY_BITS
) for x
in range(Index()))
2519 plru_victim
= PLRUOut()
2520 replace_way
= Signal(WAY_BITS
)
2522 # -- Wishbone read/write/cache write formatting signals
2523 # signal bus_sel : std_ulogic_vector(7 downto 0);
2524 # Wishbone read/write/cache write formatting signals
2528 # signal tlb_tag_way : tlb_way_tags_t;
2529 # signal tlb_pte_way : tlb_way_ptes_t;
2530 # signal tlb_valid_way : tlb_way_valids_t;
2531 # signal tlb_req_index : tlb_index_t;
2532 # signal tlb_hit : std_ulogic;
2533 # signal tlb_hit_way : tlb_way_t;
2534 # signal pte : tlb_pte_t;
2535 # signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
2536 # signal valid_ra : std_ulogic;
2537 # signal perm_attr : perm_attr_t;
2538 # signal rc_ok : std_ulogic;
2539 # signal perm_ok : std_ulogic;
2540 # signal access_ok : std_ulogic;
2542 tlb_tag_way
= Signal(TLB_WAY_TAGS
)
2543 tlb_pte_way
= Signal(TLB_WAY_PTES
)
2544 tlb_valid_way
= Signal(TLB_WAY_VALID_BITS
)
2545 tlb_req_index
= Signal(TLB_SET_SIZE
)
2547 tlb_hit_way
= Signal(TLB_WAY
)
2548 pte
= Signal(TLB_PTE
)
2549 ra
= Signal(REAL_ADDR_BITS
)
2551 perm_attr
= PermAttr()
2554 access_ok
= Signal()
2556 # -- TLB PLRU output interface
2557 # type tlb_plru_out_t is array(tlb_index_t) of
2558 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
2559 # signal tlb_plru_victim : tlb_plru_out_t;
2560 # TLB PLRU output interface
2563 Signal(TLB_WAY_BITS
) for x
in range(TLB_SET_SIZE
)
2566 tlb_plru_victim
= TLBPLRUOut()
2568 # -- Helper functions to decode incoming requests
2570 # -- Return the cache line index (tag index) for an address
2571 # function get_index(addr: std_ulogic_vector) return index_t is
2573 # return to_integer(
2574 # unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))
2577 # Helper functions to decode incoming requests
2579 # Return the cache line index (tag index) for an address
2580 def get_index(addr
):
2581 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
2583 # -- Return the cache row index (data memory) for an address
2584 # function get_row(addr: std_ulogic_vector) return row_t is
2586 # return to_integer(
2587 # unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))
2590 # Return the cache row index (data memory) for an address
2592 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
2594 # -- Return the index of a row within a line
2595 # function get_row_of_line(row: row_t) return row_in_line_t is
2596 # variable row_v : unsigned(ROW_BITS-1 downto 0);
2598 # row_v := to_unsigned(row, ROW_BITS);
2599 # return row_v(ROW_LINEBITS-1 downto 0);
2601 # Return the index of a row within a line
2602 def get_row_of_line(row
):
2603 row_v
= Signal(ROW_BITS
)
2605 return row_v
[0:ROW_LINE_BITS
]
2607 # -- Returns whether this is the last row of a line
2608 # function is_last_row_addr(addr: wishbone_addr_type;
2609 # last: row_in_line_t) return boolean is
2612 # unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
2614 # Returns whether this is the last row of a line
2615 def is_last_row_addr(addr
, last
):
2616 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
2618 # -- Returns whether this is the last row of a line
2619 # function is_last_row(row: row_t; last: row_in_line_t)
2622 # return get_row_of_line(row) = last;
2624 # Returns whether this is the last row of a line
2625 def is_last_row(row
, last
):
2626 return get_row_of_line(row
) == last
2628 # -- Return the address of the next row in the current cache line
2629 # function next_row_addr(addr: wishbone_addr_type)
2630 # return std_ulogic_vector is
2631 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
2632 # variable result : wishbone_addr_type;
2634 # -- Is there no simpler way in VHDL to
2635 # -- generate that 3 bits adder ?
2636 # row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
2637 # row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
2639 # result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
2642 # Return the address of the next row in the current cache line
2643 def next_row_addr(addr
):
2644 row_idx
= Signal(ROW_LINE_BITS
)
2645 result
= WBAddrType()
2646 # Is there no simpler way in VHDL to
2647 # generate that 3 bits adder ?
2648 row_idx
= addr
[ROW_OFF_BITS
:LINE_OFF_BITS
]
2649 row_idx
= Signal(row_idx
+ 1)
2651 result
[ROW_OFF_BITS
:LINE_OFF_BITS
] = row_idx
2654 # -- Return the next row in the current cache line. We use a
2655 # -- dedicated function in order to limit the size of the
2656 # -- generated adder to be only the bits within a cache line
2657 # -- (3 bits with default settings)
2658 # function next_row(row: row_t) return row_t is
2659 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
2660 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
2661 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
2663 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
2664 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
2665 # row_v(ROW_LINEBITS-1 downto 0) :=
2666 # std_ulogic_vector(unsigned(row_idx) + 1);
2667 # return to_integer(unsigned(row_v));
2669 # Return the next row in the current cache line. We use a
2670 # dedicated function in order to limit the size of the
2671 # generated adder to be only the bits within a cache line
2672 # (3 bits with default settings)
2674 row_v
= Signal(ROW_BITS
)
2675 row_idx
= Signal(ROW_LINE_BITS
)
2676 result
= Signal(ROW_BITS
)
2679 row_idx
= row_v
[ROW_LINE_BITS
]
2680 row_v
[0:ROW_LINE_BITS
] = Signal(row_idx
+ 1)
2683 # -- Get the tag value from the address
2684 # function get_tag(addr: std_ulogic_vector) return cache_tag_t is
2686 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
2688 # Get the tag value from the address
2690 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
2692 # -- Read a tag from a tag memory row
2693 # function read_tag(way: way_t; tagset: cache_tags_set_t)
2694 # return cache_tag_t is
2696 # return tagset(way * TAG_WIDTH + TAG_BITS
2697 # - 1 downto way * TAG_WIDTH);
2699 # Read a tag from a tag memory row
2700 def read_tag(way
, tagset
):
2701 return tagset
[way
*TAG_WIDTH
:way
* TAG_WIDTH
+ TAG_BITS
]
2703 # -- Read a TLB tag from a TLB tag memory row
2704 # function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t)
2705 # return tlb_tag_t is
2706 # variable j : integer;
2708 # j := way * TLB_EA_TAG_BITS;
2709 # return tags(j + TLB_EA_TAG_BITS - 1 downto j);
2711 # Read a TLB tag from a TLB tag memory row
2712 def read_tlb_tag(way
, tags
):
2715 j
= way
* TLB_EA_TAG_BITS
2716 return tags
[j
:j
+ TLB_EA_TAG_BITS
]
2718 # -- Write a TLB tag to a TLB tag memory row
2719 # procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
2720 # tag: tlb_tag_t) is
2721 # variable j : integer;
2723 # j := way * TLB_EA_TAG_BITS;
2724 # tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
2726 # Write a TLB tag to a TLB tag memory row
2727 def write_tlb_tag(way
, tags
), tag
):
2730 j
= way
* TLB_EA_TAG_BITS
2731 tags
[j
:j
+ TLB_EA_TAG_BITS
] = tag
2733 # -- Read a PTE from a TLB PTE memory row
2734 # function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t)
2735 # return tlb_pte_t is
2736 # variable j : integer;
2738 # j := way * TLB_PTE_BITS;
2739 # return ptes(j + TLB_PTE_BITS - 1 downto j);
2741 # Read a PTE from a TLB PTE memory row
2742 def read_tlb_pte(way
, ptes
):
2745 j
= way
* TLB_PTE_BITS
2746 return ptes
[j
:j
+ TLB_PTE_BITS
]
2748 # procedure write_tlb_pte(way: tlb_way_t;
2749 # ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
2750 # variable j : integer;
2752 # j := way * TLB_PTE_BITS;
2753 # ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
2755 def write_tlb_pte(way
, ptes
,newpte
):
2758 j
= way
* TLB_PTE_BITS
2759 return ptes
[j
:j
+ TLB_PTE_BITS
] = newpte
2763 """these, because they are constants, can actually be done *as*
2765 assert LINE_SIZE % ROWSIZE == 0, "line size not ...."
2767 # assert LINE_SIZE mod ROW_SIZE = 0
2768 # report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
2769 # assert ispow2(LINE_SIZE)
2770 # report "LINE_SIZE not power of 2" severity FAILURE;
2771 # assert ispow2(NUM_LINES)
2772 # report "NUM_LINES not power of 2" severity FAILURE;
2773 # assert ispow2(ROW_PER_LINE)
2774 # report "ROW_PER_LINE not power of 2" severity FAILURE;
2775 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
2776 # report "geometry bits don't add up" severity FAILURE;
2777 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
2778 # report "geometry bits don't add up" severity FAILURE;
2779 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
2780 # report "geometry bits don't add up" severity FAILURE;
2781 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
2782 # report "geometry bits don't add up" severity FAILURE;
2783 # assert (64 = wishbone_data_bits)
2784 # report "Can't yet handle a wishbone width that isn't 64-bits"
2786 # assert SET_SIZE_BITS <= TLB_LG_PGSZ
2787 # report "Set indexed by virtual address" severity FAILURE;
2788 assert (LINE_SIZE
% ROW_SIZE
) == 0 "LINE_SIZE not " \
2789 "multiple of ROW_SIZE"
2791 assert (LINE_SIZE
% 2) == 0 "LINE_SIZE not power of 2"
2793 assert (NUM_LINES
% 2) == 0 "NUM_LINES not power of 2"
2795 assert (ROW_PER_LINE
% 2) == 0 "ROW_PER_LINE not" \
2798 assert ROW_BITS
== (INDEX_BITS
+ ROW_LINE_BITS
) \
2799 "geometry bits don't add up"
2801 assert (LINE_OFF_BITS
= ROW_OFF_BITS
+ ROW_LINEBITS
) \
2802 "geometry bits don't add up"
2804 assert REAL_ADDR_BITS
== (TAG_BITS
+ INDEX_BITS \
2805 + LINE_OFF_BITS
) "geometry bits don't add up"
2807 assert REAL_ADDR_BITS
== (TAG_BITS
+ ROW_BITS
+ ROW_OFF_BITS
) \
2808 "geometry bits don't add up"
2810 assert 64 == wishbone_data_bits
"Can't yet handle a" \
2811 "wishbone width that isn't 64-bits"
2813 assert SET_SIZE_BITS
<= TLB_LG_PGSZ
"Set indexed by" \
2816 # -- we don't yet handle collisions between loadstore1 requests
2817 # -- and MMU requests
2818 # m_out.stall <= '0';
2819 # we don't yet handle collisions between loadstore1 requests
2821 comb
+= m_out
.stall
.eq(0)
2823 # -- Hold off the request in r0 when r1 has an uncompleted request
2824 # r0_stall <= r0_full and r1.full;
2825 # r0_valid <= r0_full and not r1.full;
2826 # stall_out <= r0_stall;
2827 # Hold off the request in r0 when r1 has an uncompleted request
2828 comb
+= r0_stall
.eq(r0_full
& r1
.full
)
2829 comb
+= r0_valid
.eq(r0_full
& ~r1
.full
)
2830 comb
+= stall_out
.eq(r0_stall
)
2833 # -- Wire up wishbone request latch out of stage 1
2834 # wishbone_out <= r1.wb;
2835 # Wire up wishbone request latch out of stage 1
2836 comb
+= wishbone_out
.eq(r1
.wb
)