3 based on Anton Blanchard microwatt icache.vhdl
7 TODO (in no specific order):
8 * Add debug interface to inspect cache content
9 * Add snoop/invalidate path
10 * Add multi-hit error detection
11 * Pipelined bus interface (wb or axi)
12 * Maybe add parity? There's a few bits free in each BRAM row on Xilinx
13 * Add optimization: service hits on partially loaded lines
14 * Add optimization: (maybe) interrupt reload on fluch/redirect
15 * Check if playing with the geometry of the cache tags allow for more
16 efficient use of distributed RAM and less logic/muxes. Currently we
17 write TAG_BITS width which may not match full ram blocks and might
18 cause muxes to be inferred for "partial writes".
19 * Check if making the read size of PLRU a ROM helps utilization
22 from enum
import Enum
, unique
23 from nmigen
import (Module
, Signal
, Elaboratable
, Cat
, Array
, Const
, Repl
)
24 from nmigen
.cli
import main
, rtlil
25 from nmutil
.iocontrol
import RecordObject
26 from nmigen
.utils
import log2_int
27 from nmutil
.util
import Display
29 #from nmutil.plru import PLRU
30 from soc
.experiment
.cache_ram
import CacheRam
31 from soc
.experiment
.plru
import PLRU
33 from soc
.experiment
.mem_types
import (Fetch1ToICacheType
,
37 from soc
.experiment
.wb_types
import (WB_ADDR_BITS
, WB_DATA_BITS
,
38 WB_SEL_BITS
, WBAddrType
, WBDataType
,
39 WBSelType
, WBMasterOut
, WBSlaveOut
,
40 WBMasterOutVector
, WBSlaveOutVector
,
41 WBIOMasterOut
, WBIOSlaveOut
)
44 from nmigen_soc
.wishbone
.sram
import SRAM
45 from nmigen
import Memory
46 from nmutil
.util
import wrap
47 from nmigen
.cli
import main
, rtlil
49 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
51 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
56 # BRAM organisation: We never access more than wishbone_data_bits
57 # at a time so to save resources we make the array only that wide,
58 # and use consecutive indices for to make a cache "line"
60 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
61 ROW_SIZE
= WB_DATA_BITS
// 8
62 # Number of lines in a set
66 # L1 ITLB number of entries (direct mapped)
68 # L1 ITLB log_2(page_size)
70 # Number of real address bits that we store
72 # Non-zero to enable log data collection
75 ROW_SIZE_BITS
= ROW_SIZE
* 8
76 # ROW_PER_LINE is the number of row
77 # (wishbone) transactions in a line
78 ROW_PER_LINE
= LINE_SIZE
// ROW_SIZE
79 # BRAM_ROWS is the number of rows in
80 # BRAM needed to represent the full icache
81 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
82 # INSN_PER_ROW is the number of 32bit
83 # instructions per BRAM row
84 INSN_PER_ROW
= ROW_SIZE_BITS
// 32
86 print("ROW_SIZE", ROW_SIZE
)
87 print("ROW_SIZE_BITS", ROW_SIZE_BITS
)
88 print("ROW_PER_LINE", ROW_PER_LINE
)
89 print("BRAM_ROWS", BRAM_ROWS
)
90 print("INSN_PER_ROW", INSN_PER_ROW
)
92 # Bit fields counts in the address
94 # INSN_BITS is the number of bits to
95 # select an instruction in a row
96 INSN_BITS
= log2_int(INSN_PER_ROW
)
97 # ROW_BITS is the number of bits to
99 ROW_BITS
= log2_int(BRAM_ROWS
)
100 # ROW_LINEBITS is the number of bits to
101 # select a row within a line
102 ROW_LINEBITS
= log2_int(ROW_PER_LINE
)
103 # LINE_OFF_BITS is the number of bits for
104 # the offset in a cache line
105 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
106 # ROW_OFF_BITS is the number of bits for
107 # the offset in a row
108 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
109 # INDEX_BITS is the number of bits to
110 # select a cache line
111 INDEX_BITS
= log2_int(NUM_LINES
)
112 # SET_SIZE_BITS is the log base 2 of
114 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
115 # TAG_BITS is the number of bits of
116 # the tag part of the address
117 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
118 # TAG_WIDTH is the width in bits of each way of the tag RAM
119 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
121 # WAY_BITS is the number of bits to
123 WAY_BITS
= log2_int(NUM_WAYS
)
124 TAG_RAM_WIDTH
= TAG_BITS
* NUM_WAYS
127 # constant TLB_BITS : natural := log2(TLB_SIZE);
128 # constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
129 # constant TLB_PTE_BITS : natural := 64;
130 TLB_BITS
= log2_int(TLB_SIZE
)
131 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_BITS
)
135 print("INSN_BITS", INSN_BITS
)
136 print("ROW_BITS", ROW_BITS
)
137 print("ROW_LINEBITS", ROW_LINEBITS
)
138 print("LINE_OFF_BITS", LINE_OFF_BITS
)
139 print("ROW_OFF_BITS", ROW_OFF_BITS
)
140 print("INDEX_BITS", INDEX_BITS
)
141 print("SET_SIZE_BITS", SET_SIZE_BITS
)
142 print("TAG_BITS", TAG_BITS
)
143 print("WAY_BITS", WAY_BITS
)
144 print("TAG_RAM_WIDTH", TAG_RAM_WIDTH
)
145 print("TLB_BITS", TLB_BITS
)
146 print("TLB_EA_TAG_BITS", TLB_EA_TAG_BITS
)
147 print("TLB_PTE_BITS", TLB_PTE_BITS
)
152 # architecture rtl of icache is
153 #constant ROW_SIZE_BITS : natural := ROW_SIZE*8;
154 #-- ROW_PER_LINE is the number of row (wishbone
155 #-- transactions) in a line
156 #constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
157 #-- BRAM_ROWS is the number of rows in BRAM
158 #-- needed to represent the full
160 #constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
161 #-- INSN_PER_ROW is the number of 32bit instructions per BRAM row
162 #constant INSN_PER_ROW : natural := ROW_SIZE_BITS / 32;
163 #-- Bit fields counts in the address
165 #-- INSN_BITS is the number of bits to select
166 #-- an instruction in a row
167 #constant INSN_BITS : natural := log2(INSN_PER_ROW);
168 #-- ROW_BITS is the number of bits to select a row
169 #constant ROW_BITS : natural := log2(BRAM_ROWS);
170 #-- ROW_LINEBITS is the number of bits to
171 #-- select a row within a line
172 #constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
173 #-- LINE_OFF_BITS is the number of bits for the offset
175 #constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
176 #-- ROW_OFF_BITS is the number of bits for the offset in a row
177 #constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
178 #-- INDEX_BITS is the number of bits to select a cache line
179 #constant INDEX_BITS : natural := log2(NUM_LINES);
180 #-- SET_SIZE_BITS is the log base 2 of the set size
181 #constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
182 #-- TAG_BITS is the number of bits of the tag part of the address
183 #constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
184 #-- WAY_BITS is the number of bits to select a way
185 #constant WAY_BITS : natural := log2(NUM_WAYS);
187 #-- Example of layout for 32 lines of 64 bytes:
189 #-- .. tag |index| line |
191 #-- .. | | | |00| zero (2)
192 #-- .. | | |-| | INSN_BITS (1)
193 #-- .. | |---| | ROW_LINEBITS (3)
194 #-- .. | |--- - --| LINE_OFF_BITS (6)
195 #-- .. | |- --| ROW_OFF_BITS (3)
196 #-- .. |----- ---| | ROW_BITS (8)
197 #-- .. |-----| | INDEX_BITS (5)
198 #-- .. --------| | TAG_BITS (53)
199 # Example of layout for 32 lines of 64 bytes:
201 # .. tag |index| line |
203 # .. | | | |00| zero (2)
204 # .. | | |-| | INSN_BITS (1)
205 # .. | |---| | ROW_LINEBITS (3)
206 # .. | |--- - --| LINE_OFF_BITS (6)
207 # .. | |- --| ROW_OFF_BITS (3)
208 # .. |----- ---| | ROW_BITS (8)
209 # .. |-----| | INDEX_BITS (5)
210 # .. --------| | TAG_BITS (53)
212 #subtype row_t is integer range 0 to BRAM_ROWS-1;
213 #subtype index_t is integer range 0 to NUM_LINES-1;
214 #subtype way_t is integer range 0 to NUM_WAYS-1;
215 #subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
217 #-- The cache data BRAM organized as described above for each way
218 #subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
220 #-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
221 #-- not handle a clean (commented) definition of the cache tags as a 3d
222 #-- memory. For now, work around it by putting all the tags
223 #subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
224 # type cache_tags_set_t is array(way_t) of cache_tag_t;
225 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
226 #constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
227 #subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
228 #type cache_tags_array_t is array(index_t) of cache_tags_set_t;
230 return Array(Signal(TAG_RAM_WIDTH
, name
="cachetag_%d" %x) \
231 for x
in range(NUM_LINES
))
233 #-- The cache valid bits
234 #subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
235 #type cache_valids_t is array(index_t) of cache_way_valids_t;
236 #type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
237 def CacheValidBitsArray():
238 return Array(Signal(NUM_WAYS
, name
="cachevalid_%d" %x) \
239 for x
in range(NUM_LINES
))
241 def RowPerLineValidArray():
242 return Array(Signal(name
="rows_valid_%d" %x) \
243 for x
in range(ROW_PER_LINE
))
246 #attribute ram_style : string;
247 #attribute ram_style of cache_tags : signal is "distributed";
248 # TODO to be passed to nigmen as ram attributes
249 # attribute ram_style : string;
250 # attribute ram_style of cache_tags : signal is "distributed";
253 #subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
254 #type tlb_valids_t is array(tlb_index_t) of std_ulogic;
255 #subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
256 #type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
257 #subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
258 #type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
259 def TLBValidBitsArray():
260 return Array(Signal(name
="tlbvalid_%d" %x) \
261 for x
in range(TLB_SIZE
))
264 return Array(Signal(TLB_EA_TAG_BITS
, name
="tlbtag_%d" %x) \
265 for x
in range(TLB_SIZE
))
268 return Array(Signal(TLB_PTE_BITS
, name
="tlbptes_%d" %x) \
269 for x
in range(TLB_SIZE
))
272 #-- Cache RAM interface
273 #type cache_ram_out_t is array(way_t) of cache_row_t;
274 # Cache RAM interface
276 return Array(Signal(ROW_SIZE_BITS
, name
="cache_out_%d" %x) \
277 for x
in range(NUM_WAYS
))
279 #-- PLRU output interface
280 #type plru_out_t is array(index_t) of
281 # std_ulogic_vector(WAY_BITS-1 downto 0);
282 # PLRU output interface
284 return Array(Signal(WAY_BITS
, name
="plru_out_%d" %x) \
285 for x
in range(NUM_LINES
))
287 # -- Return the cache line index (tag index) for an address
288 # function get_index(addr: std_ulogic_vector(63 downto 0))
291 # return to_integer(unsigned(
292 # addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)
295 # Return the cache line index (tag index) for an address
297 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
299 # -- Return the cache row index (data memory) for an address
300 # function get_row(addr: std_ulogic_vector(63 downto 0))
303 # return to_integer(unsigned(
304 # addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)
307 # Return the cache row index (data memory) for an address
309 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
311 # -- Return the index of a row within a line
312 # function get_row_of_line(row: row_t) return row_in_line_t is
313 # variable row_v : unsigned(ROW_BITS-1 downto 0);
315 # row_v := to_unsigned(row, ROW_BITS);
316 # return row_v(ROW_LINEBITS-1 downto 0);
318 # Return the index of a row within a line
319 def get_row_of_line(row
):
320 return row
[:ROW_LINEBITS
]
322 # -- Returns whether this is the last row of a line
323 # function is_last_row_addr(addr: wishbone_addr_type;
324 # last: row_in_line_t
329 # addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)
332 # Returns whether this is the last row of a line
333 def is_last_row_addr(addr
, last
):
334 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
336 # -- Returns whether this is the last row of a line
337 # function is_last_row(row: row_t;
338 # last: row_in_line_t) return boolean is
340 # return get_row_of_line(row) = last;
342 # Returns whether this is the last row of a line
343 def is_last_row(row
, last
):
344 return get_row_of_line(row
) == last
346 # -- Return the next row in the current cache line. We use a dedicated
347 # -- function in order to limit the size of the generated adder to be
348 # -- only the bits within a cache line (3 bits with default settings)
349 # function next_row(row: row_t) return row_t is
350 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
351 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
352 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
354 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
355 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
356 # row_v(ROW_LINEBITS-1 downto 0) :=
357 # std_ulogic_vector(unsigned(row_idx) + 1);
358 # return to_integer(unsigned(row_v));
360 # Return the next row in the current cache line. We use a dedicated
361 # function in order to limit the size of the generated adder to be
362 # only the bits within a cache line (3 bits with default settings)
364 row_v
= row
[0:ROW_LINEBITS
] + 1
365 return Cat(row_v
[:ROW_LINEBITS
], row
[ROW_LINEBITS
:])
366 # -- Read the instruction word for the given address in the
367 # -- current cache row
368 # function read_insn_word(addr: std_ulogic_vector(63 downto 0);
369 # data: cache_row_t) return std_ulogic_vector is
370 # variable word: integer range 0 to INSN_PER_ROW-1;
372 # word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
373 # return data(31+word*32 downto word*32);
375 # Read the instruction word for the given address
376 # in the current cache row
377 def read_insn_word(addr
, data
):
378 word
= addr
[2:INSN_BITS
+2]
379 return data
.word_select(word
, 32)
381 # -- Get the tag value from the address
383 # addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)
385 # return cache_tag_t is
387 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
389 # Get the tag value from the address
391 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
393 # -- Read a tag from a tag memory row
394 # function read_tag(way: way_t; tagset: cache_tags_set_t)
395 # return cache_tag_t is
397 # return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
399 # Read a tag from a tag memory row
400 def read_tag(way
, tagset
):
401 return tagset
.word_select(way
, TAG_BITS
)
403 # -- Write a tag to tag memory row
404 # procedure write_tag(way: in way_t;
405 # tagset: inout cache_tags_set_t; tag: cache_tag_t) is
407 # tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
409 # Write a tag to tag memory row
410 def write_tag(way
, tagset
, tag
):
411 return read_tag(way
, tagset
).eq(tag
)
413 # -- Simple hash for direct-mapped TLB index
414 # function hash_ea(addr: std_ulogic_vector(63 downto 0))
415 # return tlb_index_t is
416 # variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
418 # hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
420 # TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto
421 # TLB_LG_PGSZ + TLB_BITS
424 # TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto
425 # TLB_LG_PGSZ + 2 * TLB_BITS
427 # return to_integer(unsigned(hash));
429 # Simple hash for direct-mapped TLB index
431 hsh
= addr
[TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_BITS
] ^ addr
[
432 TLB_LG_PGSZ
+ TLB_BITS
:TLB_LG_PGSZ
+ 2 * TLB_BITS
434 TLB_LG_PGSZ
+ 2 * TLB_BITS
:TLB_LG_PGSZ
+ 3 * TLB_BITS
440 # XXX put these assert statements in - as python asserts
442 # assert LINE_SIZE mod ROW_SIZE = 0;
443 # assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2"
444 # assert ispow2(NUM_LINES) report "NUM_LINES not power of 2"
445 # assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2"
446 # assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2"
447 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
448 # report "geometry bits don't add up"
449 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
450 # report "geometry bits don't add up"
451 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
452 # report "geometry bits don't add up"
453 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
454 # report "geometry bits don't add up"
456 # sim_debug: if SIM generate
459 # report "ROW_SIZE = " & natural'image(ROW_SIZE);
460 # report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
461 # report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
462 # report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
463 # report "INSN_BITS = " & natural'image(INSN_BITS);
464 # report "ROW_BITS = " & natural'image(ROW_BITS);
465 # report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
466 # report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
467 # report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
468 # report "INDEX_BITS = " & natural'image(INDEX_BITS);
469 # report "TAG_BITS = " & natural'image(TAG_BITS);
470 # report "WAY_BITS = " & natural'image(WAY_BITS);
475 # Cache reload state machine
483 class RegInternal(RecordObject
):
486 # Cache hit state (Latches for 1 cycle BRAM access)
487 self
.hit_way
= Signal(NUM_WAYS
)
488 self
.hit_nia
= Signal(64)
489 self
.hit_smark
= Signal()
490 self
.hit_valid
= Signal()
492 # Cache miss state (reload state machine)
493 self
.state
= Signal(State
, reset
=State
.IDLE
)
494 self
.wb
= WBMasterOut("wb")
495 self
.req_adr
= Signal(64)
496 self
.store_way
= Signal(NUM_WAYS
)
497 self
.store_index
= Signal(NUM_LINES
)
498 self
.store_row
= Signal(BRAM_ROWS
)
499 self
.store_tag
= Signal(TAG_BITS
)
500 self
.store_valid
= Signal()
501 self
.end_row_ix
= Signal(ROW_LINEBITS
)
502 self
.rows_valid
= RowPerLineValidArray()
505 self
.fetch_failed
= Signal()
507 # -- 64 bit direct mapped icache. All instructions are 4B aligned.
511 # SIM : boolean := false;
512 # -- Line size in bytes
513 # LINE_SIZE : positive := 64;
514 # -- BRAM organisation: We never access more
515 # -- than wishbone_data_bits
516 # -- at a time so to save resources we make the
517 # -- array only that wide,
518 # -- and use consecutive indices for to make a cache "line"
520 # -- ROW_SIZE is the width in bytes of the BRAM (based on WB,
522 # ROW_SIZE : positive := wishbone_data_bits / 8;
523 # -- Number of lines in a set
524 # NUM_LINES : positive := 32;
526 # NUM_WAYS : positive := 4;
527 # -- L1 ITLB number of entries (direct mapped)
528 # TLB_SIZE : positive := 64;
529 # -- L1 ITLB log_2(page_size)
530 # TLB_LG_PGSZ : positive := 12;
531 # -- Number of real address bits that we store
532 # REAL_ADDR_BITS : positive := 56;
533 # -- Non-zero to enable log data collection
534 # LOG_LENGTH : natural := 0
537 # clk : in std_ulogic;
538 # rst : in std_ulogic;
540 # i_in : in Fetch1ToIcacheType;
541 # i_out : out IcacheToDecode1Type;
543 # m_in : in MmuToIcacheType;
545 # stall_in : in std_ulogic;
546 # stall_out : out std_ulogic;
547 # flush_in : in std_ulogic;
548 # inval_in : in std_ulogic;
550 # wishbone_out : out wishbone_master_out;
551 # wishbone_in : in wishbone_slave_out;
553 # log_out : out std_ulogic_vector(53 downto 0)
556 # 64 bit direct mapped icache. All instructions are 4B aligned.
557 class ICache(Elaboratable
):
558 """64 bit direct mapped icache. All instructions are 4B aligned."""
560 self
.i_in
= Fetch1ToICacheType(name
="i_in")
561 self
.i_out
= ICacheToDecode1Type(name
="i_out")
563 self
.m_in
= MMUToICacheType(name
="m_in")
565 self
.stall_in
= Signal()
566 self
.stall_out
= Signal()
567 self
.flush_in
= Signal()
568 self
.inval_in
= Signal()
570 self
.wb_out
= WBMasterOut(name
="wb_out")
571 self
.wb_in
= WBSlaveOut(name
="wb_in")
573 self
.log_out
= Signal(54)
576 # Generate a cache RAM for each way
577 def rams(self
, m
, r
, cache_out_row
, use_previous
, replace_way
, req_row
):
581 wb_in
, stall_in
= self
.wb_in
, self
.stall_in
583 for i
in range(NUM_WAYS
):
584 do_read
= Signal(name
="do_rd_%d" % i
)
585 do_write
= Signal(name
="do_wr_%d" % i
)
586 rd_addr
= Signal(ROW_BITS
)
587 wr_addr
= Signal(ROW_BITS
)
588 d_out
= Signal(ROW_SIZE_BITS
, name
="d_out_%d" % i
)
589 wr_sel
= Signal(ROW_SIZE
)
591 way
= CacheRam(ROW_BITS
, ROW_SIZE_BITS
, True)
592 setattr(m
.submodules
, "cacheram_%d" % i
, way
)
594 comb
+= way
.rd_en
.eq(do_read
)
595 comb
+= way
.rd_addr
.eq(rd_addr
)
596 comb
+= d_out
.eq(way
.rd_data_o
)
597 comb
+= way
.wr_sel
.eq(wr_sel
)
598 comb
+= way
.wr_addr
.eq(wr_addr
)
599 comb
+= way
.wr_data
.eq(wb_in
.dat
)
601 comb
+= do_read
.eq(~
(stall_in | use_previous
))
602 comb
+= do_write
.eq(wb_in
.ack
& (replace_way
== i
))
605 sync
+= Display("cache write adr: %x data: %lx",
606 wr_addr
, way
.wr_data
)
608 with m
.If(r
.hit_way
== i
):
609 comb
+= cache_out_row
.eq(d_out
)
611 sync
+= Display("cache read adr: %x data: %x",
614 comb
+= rd_addr
.eq(req_row
)
615 comb
+= wr_addr
.eq(r
.store_row
)
616 comb
+= wr_sel
.eq(Repl(do_write
, ROW_SIZE
))
619 def maybe_plrus(self
, m
, r
, plru_victim
):
622 with m
.If(NUM_WAYS
> 1):
623 for i
in range(NUM_LINES
):
624 plru_acc_i
= Signal(WAY_BITS
)
625 plru_acc_en
= Signal()
626 plru
= PLRU(WAY_BITS
)
627 setattr(m
.submodules
, "plru_%d" % i
, plru
)
629 comb
+= plru
.acc_i
.eq(plru_acc_i
)
630 comb
+= plru
.acc_en
.eq(plru_acc_en
)
633 with m
.If(get_index(r
.hit_nia
) == i
):
634 comb
+= plru
.acc_en
.eq(r
.hit_valid
)
636 comb
+= plru
.acc_i
.eq(r
.hit_way
)
637 comb
+= plru_victim
[i
].eq(plru
.lru_o
)
639 # TLB hit detection and real address generation
640 def itlb_lookup(self
, m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
641 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
642 priv_fault
, access_ok
):
647 pte
= Signal(TLB_PTE_BITS
)
648 ttag
= Signal(TLB_EA_TAG_BITS
)
650 comb
+= tlb_req_index
.eq(hash_ea(i_in
.nia
))
651 comb
+= pte
.eq(itlb_ptes
[tlb_req_index
])
652 comb
+= ttag
.eq(itlb_tags
[tlb_req_index
])
654 with m
.If(i_in
.virt_mode
):
655 comb
+= real_addr
.eq(Cat(
656 i_in
.nia
[:TLB_LG_PGSZ
],
657 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
660 with m
.If(ttag
== i_in
.nia
[TLB_LG_PGSZ
+ TLB_BITS
:64]):
661 comb
+= ra_valid
.eq(itlb_valid_bits
[tlb_req_index
])
663 comb
+= eaa_priv
.eq(pte
[3])
666 comb
+= real_addr
.eq(i_in
.nia
[:REAL_ADDR_BITS
])
667 comb
+= ra_valid
.eq(1)
668 comb
+= eaa_priv
.eq(1)
670 # No IAMR, so no KUEP support for now
671 comb
+= priv_fault
.eq(eaa_priv
& ~i_in
.priv_mode
)
672 comb
+= access_ok
.eq(ra_valid
& ~priv_fault
)
675 def itlb_update(self
, m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
):
681 wr_index
= Signal(TLB_SIZE
)
682 comb
+= wr_index
.eq(hash_ea(m_in
.addr
))
684 with m
.If(m_in
.tlbie
& m_in
.doall
):
685 # Clear all valid bits
686 for i
in range(TLB_SIZE
):
687 sync
+= itlb_valid_bits
[i
].eq(0)
689 with m
.Elif(m_in
.tlbie
):
690 # Clear entry regardless of hit or miss
691 sync
+= itlb_valid_bits
[wr_index
].eq(0)
693 with m
.Elif(m_in
.tlbld
):
694 sync
+= itlb_tags
[wr_index
].eq(
695 m_in
.addr
[TLB_LG_PGSZ
+ TLB_BITS
:64]
697 sync
+= itlb_ptes
[wr_index
].eq(m_in
.pte
)
698 sync
+= itlb_valid_bits
[wr_index
].eq(1)
700 # Cache hit detection, output to fetch2 and other misc logic
701 def icache_comb(self
, m
, use_previous
, r
, req_index
, req_row
, req_hit_way
,
702 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
703 cache_tags
, access_ok
, req_is_hit
,
704 req_is_miss
, replace_way
, plru_victim
, cache_out_row
):
707 #comb += Display("ENTER icache_comb - use_previous:%x req_index:%x "
708 # "req_row:%x req_tag:%x real_addr:%x req_laddr:%x "
709 # "access_ok:%x req_is_hit:%x req_is_miss:%x "
710 # "replace_way:%x", use_previous, req_index, req_row,
711 # req_tag, real_addr, req_laddr, access_ok,
712 # req_is_hit, req_is_miss, replace_way)
714 i_in
, i_out
, wb_out
= self
.i_in
, self
.i_out
, self
.wb_out
715 flush_in
, stall_out
= self
.flush_in
, self
.stall_out
718 hit_way
= Signal(NUM_WAYS
)
720 # i_in.sequential means that i_in.nia this cycle is 4 more than
721 # last cycle. If we read more than 32 bits at a time, had a
722 # cache hit last cycle, and we don't want the first 32-bit chunk
723 # then we can keep the data we read last cycle and just use that.
724 with m
.If(i_in
.nia
[2:INSN_BITS
+2] != 0):
725 comb
+= use_previous
.eq(i_in
.sequential
& r
.hit_valid
)
727 # Extract line, row and tag from request
728 comb
+= req_index
.eq(get_index(i_in
.nia
))
729 comb
+= req_row
.eq(get_row(i_in
.nia
))
730 comb
+= req_tag
.eq(get_tag(real_addr
))
732 # Calculate address of beginning of cache row, will be
733 # used for cache miss processing if needed
734 comb
+= req_laddr
.eq(Cat(
735 Const(0, ROW_OFF_BITS
),
736 real_addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
],
739 # Test if pending request is a hit on any way
741 comb
+= hitcond
.eq((r
.state
== State
.WAIT_ACK
)
742 & (req_index
== r
.store_index
)
743 & r
.rows_valid
[req_row
% ROW_PER_LINE
])
745 cvb
= Signal(NUM_WAYS
)
746 ctag
= Signal(TAG_RAM_WIDTH
)
747 comb
+= ctag
.eq(cache_tags
[req_index
])
748 comb
+= cvb
.eq(cache_valid_bits
[req_index
])
749 for i
in range(NUM_WAYS
):
750 tagi
= Signal(TAG_BITS
, name
="ti%d" % i
)
751 comb
+= tagi
.eq(read_tag(i
, ctag
))
752 hit_test
= Signal(name
="hit_test%d" % i
)
753 comb
+= hit_test
.eq(i
== r
.store_way
)
754 with m
.If((cvb
[i
] |
(hitcond
& hit_test
)) & (tagi
== req_tag
)):
755 comb
+= hit_way
.eq(i
)
758 # Generate the "hit" and "miss" signals
759 # for the synchronous blocks
760 with m
.If(i_in
.req
& access_ok
& ~flush_in
):
761 comb
+= req_is_hit
.eq(is_hit
)
762 comb
+= req_is_miss
.eq(~is_hit
)
765 comb
+= req_is_hit
.eq(0)
766 comb
+= req_is_miss
.eq(0)
768 comb
+= req_hit_way
.eq(hit_way
)
770 # The way to replace on a miss
771 with m
.If(r
.state
== State
.CLR_TAG
):
772 comb
+= replace_way
.eq(plru_victim
[r
.store_index
])
774 comb
+= replace_way
.eq(r
.store_way
)
776 # Output instruction from current cache row
778 # Note: This is a mild violation of our design principle of
779 # having pipeline stages output from a clean latch. In this
780 # case we output the result of a mux. The alternative would
781 # be output an entire row which I prefer not to do just yet
782 # as it would force fetch2 to know about some of the cache
783 # geometry information.
784 #comb += Display("BEFORE read_insn_word - r.hit_nia:%x " \
785 # "r.hit_way:%x, cache_out[r.hit_way]:%x", r.hit_nia, \
786 # r.hit_way, cache_out[r.hit_way])
787 comb
+= i_out
.insn
.eq(read_insn_word(r
.hit_nia
, cache_out_row
))
788 comb
+= i_out
.valid
.eq(r
.hit_valid
)
789 comb
+= i_out
.nia
.eq(r
.hit_nia
)
790 comb
+= i_out
.stop_mark
.eq(r
.hit_smark
)
791 comb
+= i_out
.fetch_failed
.eq(r
.fetch_failed
)
793 # Stall fetch1 if we have a miss on cache or TLB
794 # or a protection fault
795 comb
+= stall_out
.eq(~
(is_hit
& access_ok
))
797 # Wishbone requests output (from the cache miss reload machine)
798 comb
+= wb_out
.eq(r
.wb
)
800 # Cache hit synchronous machine
801 def icache_hit(self
, m
, use_previous
, r
, req_is_hit
, req_hit_way
,
802 req_index
, req_tag
, real_addr
):
805 i_in
, stall_in
= self
.i_in
, self
.stall_in
806 flush_in
= self
.flush_in
808 # keep outputs to fetch2 unchanged on a stall
809 # except that flush or reset sets valid to 0
810 # If use_previous, keep the same data as last
811 # cycle and use the second half
812 with m
.If(stall_in | use_previous
):
814 sync
+= r
.hit_valid
.eq(0)
816 # On a hit, latch the request for the next cycle,
817 # when the BRAM data will be available on the
818 # cache_out output of the corresponding way
819 sync
+= r
.hit_valid
.eq(req_is_hit
)
821 with m
.If(req_is_hit
):
822 sync
+= r
.hit_way
.eq(req_hit_way
)
823 sync
+= Display("cache hit nia:%x IR:%x SM:%x idx:%x " \
824 "tag:%x way:%x RA:%x", i_in
.nia
, \
825 i_in
.virt_mode
, i_in
.stop_mark
, req_index
, \
826 req_tag
, req_hit_way
, real_addr
)
830 with m
.If(~stall_in
):
831 # Send stop marks and NIA down regardless of validity
832 sync
+= r
.hit_smark
.eq(i_in
.stop_mark
)
833 sync
+= r
.hit_nia
.eq(i_in
.nia
)
835 # Cache miss/reload synchronous machine
836 def icache_miss(self
, m
, cache_valid_bits
, r
, req_is_miss
,
837 req_index
, req_laddr
, req_tag
, replace_way
,
838 cache_tags
, access_ok
, real_addr
):
842 i_in
, wb_in
, m_in
= self
.i_in
, self
.wb_in
, self
.m_in
843 stall_in
, flush_in
= self
.stall_in
, self
.flush_in
844 inval_in
= self
.inval_in
846 # variable tagset : cache_tags_set_t;
847 # variable stbs_done : boolean;
849 tagset
= Signal(TAG_RAM_WIDTH
)
852 comb
+= r
.wb
.sel
.eq(-1)
853 comb
+= r
.wb
.adr
.eq(r
.req_adr
[3:])
855 # Process cache invalidations
857 for i
in range(NUM_LINES
):
858 sync
+= cache_valid_bits
[i
].eq(0)
859 sync
+= r
.store_valid
.eq(0)
862 with m
.Switch(r
.state
):
864 with m
.Case(State
.IDLE
):
865 # Reset per-row valid flags,
866 # only used in WAIT_ACK
867 for i
in range(ROW_PER_LINE
):
868 sync
+= r
.rows_valid
[i
].eq(0)
870 # We need to read a cache line
871 with m
.If(req_is_miss
):
872 sync
+= Display("cache miss nia:%x IR:%x SM:%x idx:%x "
873 " way:%x tag:%x RA:%x", i_in
.nia
,
874 i_in
.virt_mode
, i_in
.stop_mark
, req_index
,
875 replace_way
, req_tag
, real_addr
)
877 # Keep track of our index and way
878 # for subsequent stores
879 st_row
= Signal(BRAM_ROWS
)
880 comb
+= st_row
.eq(get_row(req_laddr
))
881 sync
+= r
.store_index
.eq(req_index
)
882 sync
+= r
.store_row
.eq(st_row
)
883 sync
+= r
.store_tag
.eq(req_tag
)
884 sync
+= r
.store_valid
.eq(1)
885 sync
+= r
.end_row_ix
.eq(get_row_of_line(st_row
) - 1)
887 # Prep for first wishbone read. We calculate the
888 # address of the start of the cache line and
889 # start the WB cycle.
890 sync
+= r
.req_adr
.eq(req_laddr
)
891 sync
+= r
.wb
.cyc
.eq(1)
892 sync
+= r
.wb
.stb
.eq(1)
894 # Track that we had one request sent
895 sync
+= r
.state
.eq(State
.CLR_TAG
)
897 with m
.Case(State
.CLR_TAG
, State
.WAIT_ACK
):
898 with m
.If(r
.state
== State
.CLR_TAG
):
899 # Get victim way from plru
900 sync
+= r
.store_way
.eq(replace_way
)
901 # Force misses on that way while reloading that line
902 cv
= Signal(INDEX_BITS
)
903 comb
+= cv
.eq(cache_valid_bits
[req_index
])
904 comb
+= cv
.bit_select(replace_way
, 1).eq(0)
905 sync
+= cache_valid_bits
[req_index
].eq(cv
)
907 for i
in range(NUM_WAYS
):
908 with m
.If(i
== replace_way
):
909 comb
+= tagset
.eq(cache_tags
[r
.store_index
])
910 comb
+= write_tag(i
, tagset
, r
.store_tag
)
911 sync
+= cache_tags
[r
.store_index
].eq(tagset
)
913 sync
+= r
.state
.eq(State
.WAIT_ACK
)
915 # Requests are all sent if stb is 0
917 comb
+= stbs_zero
.eq(r
.wb
.stb
== 0)
918 comb
+= stbs_done
.eq(stbs_zero
)
920 # If we are still sending requests, was one accepted?
921 with m
.If(~wb_in
.stall
& ~stbs_zero
):
922 # That was the last word ? # We are done sending.
923 # Clear stb and set stbs_done # so we can handle
924 # an eventual last ack on # the same cycle.
925 with m
.If(is_last_row_addr(r
.req_adr
, r
.end_row_ix
)):
926 sync
+= Display("IS_LAST_ROW_ADDR " \
927 "r.wb.addr:%x r.end_row_ix:%x " \
928 "r.wb.stb:%x stbs_zero:%x " \
929 "stbs_done:%x", r
.wb
.adr
, \
930 r
.end_row_ix
, r
.wb
.stb
, \
931 stbs_zero
, stbs_done
)
932 sync
+= r
.wb
.stb
.eq(0)
933 comb
+= stbs_done
.eq(1)
935 # Calculate the next row address
936 rarange
= Signal(LINE_OFF_BITS
- ROW_OFF_BITS
)
938 r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
] + 1
940 sync
+= r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
].eq(
943 sync
+= Display("RARANGE r.req_adr:%x rarange:%x "
944 "stbs_zero:%x stbs_done:%x",
945 r
.req_adr
, rarange
, stbs_zero
, stbs_done
)
947 # Incoming acks processing
948 with m
.If(wb_in
.ack
):
949 sync
+= Display("WB_IN_ACK data:%x stbs_zero:%x "
951 wb_in
.dat
, stbs_zero
, stbs_done
)
953 sync
+= r
.rows_valid
[r
.store_row
% ROW_PER_LINE
].eq(1)
955 # Check for completion
956 with m
.If(stbs_done
&
957 is_last_row(r
.store_row
, r
.end_row_ix
)):
958 # Complete wishbone cycle
959 sync
+= r
.wb
.cyc
.eq(0)
960 sync
+= r
.req_adr
.eq(0) # be nice, clear addr
962 # Cache line is now valid
963 cv
= Signal(INDEX_BITS
)
964 comb
+= cv
.eq(cache_valid_bits
[r
.store_index
])
965 comb
+= cv
.bit_select(replace_way
, 1).eq(
966 r
.store_valid
& ~inval_in
968 sync
+= cache_valid_bits
[r
.store_index
].eq(cv
)
970 sync
+= r
.state
.eq(State
.IDLE
)
972 # not completed, move on to next request in row
974 # Increment store row counter
975 sync
+= r
.store_row
.eq(next_row(r
.store_row
))
977 # TLB miss and protection fault processing
978 with m
.If(flush_in | m_in
.tlbld
):
979 sync
+= r
.fetch_failed
.eq(0)
980 with m
.Elif(i_in
.req
& ~access_ok
& ~stall_in
):
981 sync
+= r
.fetch_failed
.eq(1)
983 # icache_log: if LOG_LENGTH > 0 generate
984 def icache_log(self
, m
, req_hit_way
, ra_valid
, access_ok
,
985 req_is_miss
, req_is_hit
, lway
, wstate
, r
):
989 wb_in
, i_out
= self
.wb_in
, self
.i_out
990 log_out
, stall_out
= self
.log_out
, self
.stall_out
992 # -- Output data to logger
993 # signal log_data : std_ulogic_vector(53 downto 0);
995 # data_log: process(clk)
996 # variable lway: way_t;
997 # variable wstate: std_ulogic;
998 # Output data to logger
999 for i
in range(LOG_LENGTH
):
1000 # Output data to logger
1001 log_data
= Signal(54)
1002 lway
= Signal(NUM_WAYS
)
1006 # if rising_edge(clk) then
1007 # lway := req_hit_way;
1009 sync
+= lway
.eq(req_hit_way
)
1010 sync
+= wstate
.eq(0)
1012 # if r.state /= IDLE then
1015 with m
.If(r
.state
!= State
.IDLE
):
1016 sync
+= wstate
.eq(1)
1018 # log_data <= i_out.valid &
1021 # r.wb.adr(5 downto 3) &
1022 # r.wb.stb & r.wb.cyc &
1023 # wishbone_in.stall &
1026 # r.hit_nia(5 downto 2) &
1028 # std_ulogic_vector(to_unsigned(lway, 3)) &
1029 # req_is_hit & req_is_miss &
1032 sync
+= log_data
.eq(Cat(
1033 ra_valid
, access_ok
, req_is_miss
, req_is_hit
,
1034 lway
, wstate
, r
.hit_nia
[2:6],
1035 r
.fetch_failed
, stall_out
, wb_in
.stall
, r
.wb
.cyc
,
1036 r
.wb
.stb
, r
.wb
.adr
[3:6], wb_in
.ack
, i_out
.insn
,
1041 # log_out <= log_data;
1042 comb
+= log_out
.eq(log_data
)
1046 def elaborate(self
, platform
):
1051 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1052 cache_tags
= CacheTagArray()
1053 cache_valid_bits
= CacheValidBitsArray()
1055 # signal itlb_valids : tlb_valids_t;
1056 # signal itlb_tags : tlb_tags_t;
1057 # signal itlb_ptes : tlb_ptes_t;
1058 # attribute ram_style of itlb_tags : signal is "distributed";
1059 # attribute ram_style of itlb_ptes : signal is "distributed";
1060 itlb_valid_bits
= TLBValidBitsArray()
1061 itlb_tags
= TLBTagArray()
1062 itlb_ptes
= TLBPtesArray()
1063 # TODO to be passed to nmigen as ram attributes
1064 # attribute ram_style of itlb_tags : signal is "distributed";
1065 # attribute ram_style of itlb_ptes : signal is "distributed";
1067 # -- Privilege bit from PTE EAA field
1068 # signal eaa_priv : std_ulogic;
1069 # Privilege bit from PTE EAA field
1072 # signal r : reg_internal_t;
1075 # -- Async signals on incoming request
1076 # signal req_index : index_t;
1077 # signal req_row : row_t;
1078 # signal req_hit_way : way_t;
1079 # signal req_tag : cache_tag_t;
1080 # signal req_is_hit : std_ulogic;
1081 # signal req_is_miss : std_ulogic;
1082 # signal req_laddr : std_ulogic_vector(63 downto 0);
1083 # Async signal on incoming request
1084 req_index
= Signal(NUM_LINES
)
1085 req_row
= Signal(BRAM_ROWS
)
1086 req_hit_way
= Signal(NUM_WAYS
)
1087 req_tag
= Signal(TAG_BITS
)
1088 req_is_hit
= Signal()
1089 req_is_miss
= Signal()
1090 req_laddr
= Signal(64)
1092 # signal tlb_req_index : tlb_index_t;
1093 # signal real_addr : std_ulogic_vector(
1094 # REAL_ADDR_BITS - 1 downto 0
1096 # signal ra_valid : std_ulogic;
1097 # signal priv_fault : std_ulogic;
1098 # signal access_ok : std_ulogic;
1099 # signal use_previous : std_ulogic;
1100 tlb_req_index
= Signal(TLB_SIZE
)
1101 real_addr
= Signal(REAL_ADDR_BITS
)
1103 priv_fault
= Signal()
1104 access_ok
= Signal()
1105 use_previous
= Signal()
1107 # signal cache_out : cache_ram_out_t;
1108 cache_out_row
= Signal(ROW_SIZE_BITS
)
1110 # signal plru_victim : plru_out_t;
1111 # signal replace_way : way_t;
1112 plru_victim
= PLRUOut()
1113 replace_way
= Signal(NUM_WAYS
)
1115 # call sub-functions putting everything together, using shared
1116 # signals established above
1117 self
.rams(m
, r
, cache_out_row
, use_previous
, replace_way
, req_row
)
1118 self
.maybe_plrus(m
, r
, plru_victim
)
1119 self
.itlb_lookup(m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
1120 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
1121 priv_fault
, access_ok
)
1122 self
.itlb_update(m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
)
1123 self
.icache_comb(m
, use_previous
, r
, req_index
, req_row
, req_hit_way
,
1124 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
1125 cache_tags
, access_ok
, req_is_hit
, req_is_miss
,
1126 replace_way
, plru_victim
, cache_out_row
)
1127 self
.icache_hit(m
, use_previous
, r
, req_is_hit
, req_hit_way
,
1128 req_index
, req_tag
, real_addr
)
1129 self
.icache_miss(m
, cache_valid_bits
, r
, req_is_miss
, req_index
,
1130 req_laddr
, req_tag
, replace_way
, cache_tags
,
1131 access_ok
, real_addr
)
1132 #self.icache_log(m, log_out, req_hit_way, ra_valid, access_ok,
1133 # req_is_miss, req_is_hit, lway, wstate, r)
1141 # use ieee.std_logic_1164.all;
1144 # use work.common.all;
1145 # use work.wishbone_types.all;
1147 # entity icache_tb is
1150 # architecture behave of icache_tb is
1151 # signal clk : std_ulogic;
1152 # signal rst : std_ulogic;
1154 # signal i_out : Fetch1ToIcacheType;
1155 # signal i_in : IcacheToDecode1Type;
1157 # signal m_out : MmuToIcacheType;
1159 # signal wb_bram_in : wishbone_master_out;
1160 # signal wb_bram_out : wishbone_slave_out;
1162 # constant clk_period : time := 10 ns;
1164 # icache0: entity work.icache
1178 # wishbone_out => wb_bram_in,
1179 # wishbone_in => wb_bram_out
1182 # -- BRAM Memory slave
1183 # bram0: entity work.wishbone_bram_wrapper
1185 # MEMORY_SIZE => 1024,
1186 # RAM_INIT_FILE => "icache_test.bin"
1191 # wishbone_in => wb_bram_in,
1192 # wishbone_out => wb_bram_out
1195 # clk_process: process
1198 # wait for clk_period/2;
1200 # wait for clk_period/2;
1203 # rst_process: process
1206 # wait for 2*clk_period;
1214 # i_out.nia <= (others => '0');
1215 # i_out.stop_mark <= '0';
1217 # m_out.tlbld <= '0';
1218 # m_out.tlbie <= '0';
1219 # m_out.addr <= (others => '0');
1220 # m_out.pte <= (others => '0');
1222 # wait until rising_edge(clk);
1223 # wait until rising_edge(clk);
1224 # wait until rising_edge(clk);
1225 # wait until rising_edge(clk);
1228 # i_out.nia <= x"0000000000000004";
1230 # wait for 30*clk_period;
1231 # wait until rising_edge(clk);
1233 # assert i_in.valid = '1' severity failure;
1234 # assert i_in.insn = x"00000001"
1235 # report "insn @" & to_hstring(i_out.nia) &
1236 # "=" & to_hstring(i_in.insn) &
1237 # " expected 00000001"
1242 # wait until rising_edge(clk);
1246 # i_out.nia <= x"0000000000000008";
1247 # wait until rising_edge(clk);
1248 # wait until rising_edge(clk);
1249 # assert i_in.valid = '1' severity failure;
1250 # assert i_in.insn = x"00000002"
1251 # report "insn @" & to_hstring(i_out.nia) &
1252 # "=" & to_hstring(i_in.insn) &
1253 # " expected 00000002"
1255 # wait until rising_edge(clk);
1259 # i_out.nia <= x"0000000000000040";
1261 # wait for 30*clk_period;
1262 # wait until rising_edge(clk);
1264 # assert i_in.valid = '1' severity failure;
1265 # assert i_in.insn = x"00000010"
1266 # report "insn @" & to_hstring(i_out.nia) &
1267 # "=" & to_hstring(i_in.insn) &
1268 # " expected 00000010"
1271 # -- test something that aliases
1273 # i_out.nia <= x"0000000000000100";
1274 # wait until rising_edge(clk);
1275 # wait until rising_edge(clk);
1276 # assert i_in.valid = '0' severity failure;
1277 # wait until rising_edge(clk);
1279 # wait for 30*clk_period;
1280 # wait until rising_edge(clk);
1282 # assert i_in.valid = '1' severity failure;
1283 # assert i_in.insn = x"00000040"
1284 # report "insn @" & to_hstring(i_out.nia) &
1285 # "=" & to_hstring(i_in.insn) &
1286 # " expected 00000040"
1294 def icache_sim(dut
):
1299 yield i_in
.valid
.eq(0)
1300 yield i_out
.priv_mode
.eq(1)
1301 yield i_out
.req
.eq(0)
1302 yield i_out
.nia
.eq(0)
1303 yield i_out
.stop_mark
.eq(0)
1304 yield m_out
.tlbld
.eq(0)
1305 yield m_out
.tlbie
.eq(0)
1306 yield m_out
.addr
.eq(0)
1307 yield m_out
.pte
.eq(0)
1312 yield i_out
.req
.eq(1)
1313 yield i_out
.nia
.eq(Const(0x0000000000000004, 64))
1317 valid
= yield i_in
.valid
1318 nia
= yield i_out
.nia
1319 insn
= yield i_in
.insn
1320 print(f
"valid? {valid}")
1322 assert insn
== 0x00000001, \
1323 "insn @%x=%x expected 00000001" % (nia
, insn
)
1324 yield i_out
.req
.eq(0)
1330 yield i_out
.req
.eq(1)
1331 yield i_out
.nia
.eq(Const(0x0000000000000008, 64))
1334 valid
= yield i_in
.valid
1335 nia
= yield i_in
.nia
1336 insn
= yield i_in
.insn
1338 assert insn
== 0x00000002, \
1339 "insn @%x=%x expected 00000002" % (nia
, insn
)
1343 yield i_out
.req
.eq(1)
1344 yield i_out
.nia
.eq(Const(0x0000000000000040, 64))
1348 valid
= yield i_in
.valid
1349 nia
= yield i_out
.nia
1350 insn
= yield i_in
.insn
1352 assert insn
== 0x00000010, \
1353 "insn @%x=%x expected 00000010" % (nia
, insn
)
1355 # test something that aliases
1356 yield i_out
.req
.eq(1)
1357 yield i_out
.nia
.eq(Const(0x0000000000000100, 64))
1360 valid
= yield i_in
.valid
1365 insn
= yield i_in
.insn
1366 valid
= yield i_in
.valid
1367 insn
= yield i_in
.insn
1369 assert insn
== 0x00000040, \
1370 "insn @%x=%x expected 00000040" % (nia
, insn
)
1371 yield i_out
.req
.eq(0)
1375 def test_icache(mem
):
1378 memory
= Memory(width
=64, depth
=512, init
=mem
)
1379 sram
= SRAM(memory
=memory
, granularity
=8)
1383 m
.submodules
.icache
= dut
1384 m
.submodules
.sram
= sram
1386 m
.d
.comb
+= sram
.bus
.cyc
.eq(dut
.wb_out
.cyc
)
1387 m
.d
.comb
+= sram
.bus
.stb
.eq(dut
.wb_out
.stb
)
1388 m
.d
.comb
+= sram
.bus
.we
.eq(dut
.wb_out
.we
)
1389 m
.d
.comb
+= sram
.bus
.sel
.eq(dut
.wb_out
.sel
)
1390 m
.d
.comb
+= sram
.bus
.adr
.eq(dut
.wb_out
.adr
)
1391 m
.d
.comb
+= sram
.bus
.dat_w
.eq(dut
.wb_out
.dat
)
1393 m
.d
.comb
+= dut
.wb_in
.ack
.eq(sram
.bus
.ack
)
1394 m
.d
.comb
+= dut
.wb_in
.dat
.eq(sram
.bus
.dat_r
)
1400 sim
.add_sync_process(wrap(icache_sim(dut
)))
1401 with sim
.write_vcd('test_icache.vcd'):
1404 if __name__
== '__main__':
1406 vl
= rtlil
.convert(dut
, ports
=[])
1407 with
open("test_icache.il", "w") as f
:
1411 for i
in range(512):
1412 mem
.append((i
*2)|
((i
*2+1)<<32))