1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from nmigen
.compat
.sim
import run_simulation
, Settle
14 from nmigen
.cli
import rtlil
15 from nmigen
import Module
17 from soc
.decoder
.power_enums
import InternalOp
19 from soc
.experiment
.compalu_multi
import MultiCompUnit
20 from soc
.experiment
.alu_hier
import ALU
, DummyALU
21 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
24 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
25 yield dut
.issue_i
.eq(0)
27 yield dut
.src_i
[0].eq(a
)
28 yield dut
.src_i
[1].eq(b
)
29 yield dut
.oper_i
.insn_type
.eq(op
)
30 yield dut
.oper_i
.invert_a
.eq(inv_a
)
31 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
32 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
33 yield dut
.oper_i
.zero_a
.eq(zero_a
)
34 yield dut
.issue_i
.eq(1)
36 yield dut
.issue_i
.eq(0)
38 if not imm_ok
or not zero_a
:
39 yield dut
.rd
.go
.eq(0b11)
42 rd_rel_o
= yield dut
.rd
.rel
43 print ("rd_rel", rd_rel_o
)
47 if len(dut
.src_i
) == 3:
48 yield dut
.rd
.go
.eq(0b100)
51 rd_rel_o
= yield dut
.rd
.rel
52 print ("rd_rel", rd_rel_o
)
57 req_rel_o
= yield dut
.wr
.rel
58 result
= yield dut
.data_o
59 print ("req_rel", req_rel_o
, result
)
61 req_rel_o
= yield dut
.wr
.rel
62 result
= yield dut
.data_o
63 print ("req_rel", req_rel_o
, result
)
67 yield dut
.wr
.go
[0].eq(1)
69 result
= yield dut
.data_o
71 print ("result", result
)
72 yield dut
.wr
.go
[0].eq(0)
77 def scoreboard_sim_dummy(dut
):
78 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_NOP
, inv_a
=0,
80 assert result
== 5, result
82 result
= yield from op_sim(dut
, 9, 2, InternalOp
.OP_NOP
, inv_a
=0,
84 assert result
== 9, result
87 def scoreboard_sim(dut
):
88 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=0,
92 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
)
95 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=1)
96 assert result
== 65532
98 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, zero_a
=1,
102 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, zero_a
=1)
105 # test combinatorial zero-delay operation
106 # In the test ALU, any operation other than ADD, MUL or SHR
107 # is zero-delay, and do a subtraction.
108 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_NOP
)
116 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
117 m
.submodules
.cu
= dut
119 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
120 with
open("test_compunit1.il", "w") as f
:
123 run_simulation(m
, scoreboard_sim(dut
), vcd_name
='test_compunit1.vcd')
126 class CompUnitParallelTest
:
127 def __init__(self
, dut
):
130 # Operation cycle should not take longer than this:
131 self
.MAX_BUSY_WAIT
= 50
133 # Minimum duration in which issue_i will be kept inactive,
134 # during which busy_o must remain low.
135 self
.MIN_BUSY_LOW
= 5
137 # Number of cycles to stall until the assertion of go.
138 # One value, for each port. Can be zero, for no delay.
139 self
.RD_GO_DELAY
= [0, 3]
141 # store common data for the input operation of the processes
144 self
.inv_a
= self
.zero_a
= 0
145 self
.imm
= self
.imm_ok
= 0
146 self
.imm_control
= (0, 0)
147 self
.rdmaskn
= (0, 0)
149 self
.operands
= (0, 0)
151 # Indicates completion of the sub-processes
152 self
.rd_complete
= [False, False]
155 print("Begin parallel test.")
156 yield from self
.operation(5, 2, InternalOp
.OP_NOP
, inv_a
=0,
157 imm
=8, imm_ok
=0, rdmaskn
=(1, 0))
159 def operation(self
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0,
161 # store data for the operation
162 self
.operands
= (a
, b
)
168 self
.imm_control
= (zero_a
, imm_ok
)
169 self
.rdmaskn
= rdmaskn
171 # Initialize completion flags
172 self
.rd_complete
= [False, False]
174 # trigger operation cycle
175 yield from self
.issue()
177 # check that the sub-processes completed, before the busy_o cycle ended
178 for completion
in self
.rd_complete
:
182 # issue_i starts inactive
183 yield self
.dut
.issue_i
.eq(0)
185 for n
in range(self
.MIN_BUSY_LOW
):
187 # busy_o must remain inactive. It cannot rise on its own.
188 busy_o
= yield self
.dut
.busy_o
191 # activate issue_i to begin the operation cycle
192 yield self
.dut
.issue_i
.eq(1)
194 # at the same time, present the operation
195 yield self
.dut
.oper_i
.insn_type
.eq(self
.op
)
196 yield self
.dut
.oper_i
.invert_a
.eq(self
.inv_a
)
197 yield self
.dut
.oper_i
.imm_data
.imm
.eq(self
.imm
)
198 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(self
.imm_ok
)
199 yield self
.dut
.oper_i
.zero_a
.eq(self
.zero_a
)
200 rdmaskn
= self
.rdmaskn
[0] |
(self
.rdmaskn
[1] << 1)
201 yield self
.dut
.rdmaskn
.eq(rdmaskn
)
203 # give one cycle for the CompUnit to latch the data
206 # busy_o must keep being low in this cycle, because issue_i was
207 # low on the previous cycle.
208 # It cannot rise on its own.
209 # Also, busy_o and issue_i must never be active at the same time, ever.
210 busy_o
= yield self
.dut
.busy_o
214 yield self
.dut
.issue_i
.eq(0)
216 # deactivate inputs along with issue_i, so we can be sure the data
217 # was latched at the correct cycle
218 # note: rdmaskn must be held, while busy_o is active
219 # TODO: deactivate rdmaskn when the busy_o cycle ends
220 yield self
.dut
.oper_i
.insn_type
.eq(0)
221 yield self
.dut
.oper_i
.invert_a
.eq(0)
222 yield self
.dut
.oper_i
.imm_data
.imm
.eq(0)
223 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(0)
224 yield self
.dut
.oper_i
.zero_a
.eq(0)
227 # wait for busy_o to lower
228 # timeout after self.MAX_BUSY_WAIT cycles
229 for n
in range(self
.MAX_BUSY_WAIT
):
230 # sample busy_o in the current cycle
231 busy_o
= yield self
.dut
.busy_o
233 # operation cycle ends when busy_o becomes inactive
237 # if busy_o is still active, a timeout has occurred
238 # TODO: Uncomment this, once the test is complete:
242 print("If you are reading this, "
243 "it's because the above test failed, as expected,\n"
244 "with a timeout. It must pass, once the test is complete.")
247 print("If you are reading this, "
248 "it's because the above test unexpectedly passed.")
250 def rd(self
, rd_idx
):
251 # wait for issue_i to rise
253 issue_i
= yield self
.dut
.issue_i
256 # issue_i has not risen yet, so rd must keep low
257 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
261 # we do not want rd to rise on an immediate operand
262 # if it is immediate, exit the process
263 # likewise, if the read mask is active
264 # TODO: don't exit the process, monitor rd instead to ensure it
265 # doesn't rise on its own
266 if self
.rdmaskn
[rd_idx
] or self
.imm_control
[rd_idx
]:
267 self
.rd_complete
[rd_idx
] = True
270 # issue_i has risen. rel must rise on the next cycle
271 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
274 # stall for additional cycles. Check that rel doesn't fall on its own
275 for n
in range(self
.RD_GO_DELAY
[rd_idx
]):
277 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
280 # Before asserting "go", make sure "rel" has risen.
281 # The use of Settle allows "go" to be set combinatorially,
282 # rising on the same cycle as "rel".
284 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
287 # assert go for one cycle, passing along the operand value
288 yield self
.dut
.rd
.go
[rd_idx
].eq(1)
289 yield self
.dut
.src_i
[rd_idx
].eq(self
.operands
[rd_idx
])
290 # check that the operand was sent to the alu
291 # TODO: Properly check the alu protocol
293 alu_input
= yield self
.dut
.get_in(rd_idx
)
294 assert alu_input
== self
.operands
[rd_idx
]
297 # rel must keep high, since go was inactive in the last cycle
298 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
301 # finish the go one-clock pulse
302 yield self
.dut
.rd
.go
[rd_idx
].eq(0)
303 yield self
.dut
.src_i
[rd_idx
].eq(0)
306 # rel must have gone low in response to go being high
307 # on the previous cycle
308 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
311 self
.rd_complete
[rd_idx
] = True
313 # TODO: check that rel doesn't rise again until the end of the
316 def wr(self
, wr_idx
):
317 # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
319 # TODO: also when dut.wr.go is set, check the output against the
320 # self.expected_o and assert. use dut.get_out(wr_idx) to do so.
322 def run_simulation(self
, vcd_name
):
323 run_simulation(self
.dut
, [self
.driver(),
324 self
.rd(0), # one read port (a)
325 self
.rd(1), # one read port (b)
326 self
.wr(0), # one write port (o)
331 def test_compunit_regspec3():
333 inspec
= [('INT', 'a', '0:15'),
334 ('INT', 'b', '0:15'),
335 ('INT', 'c', '0:15')]
336 outspec
= [('INT', 'o', '0:15'),
339 regspec
= (inspec
, outspec
)
343 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
344 m
.submodules
.cu
= dut
346 run_simulation(m
, scoreboard_sim_dummy(dut
),
347 vcd_name
='test_compunit_regspec3.vcd')
350 def test_compunit_regspec1():
352 inspec
= [('INT', 'a', '0:15'),
353 ('INT', 'b', '0:15')]
354 outspec
= [('INT', 'o', '0:15'),
357 regspec
= (inspec
, outspec
)
361 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
362 m
.submodules
.cu
= dut
364 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
365 with
open("test_compunit_regspec1.il", "w") as f
:
368 run_simulation(m
, scoreboard_sim(dut
),
369 vcd_name
='test_compunit_regspec1.vcd')
371 test
= CompUnitParallelTest(dut
)
372 test
.run_simulation("test_compunit_parallel.vcd")
375 if __name__
== '__main__':
377 test_compunit_regspec1()
378 test_compunit_regspec3()