src/soc/experiment/test/test_dcbz_pi.py

   1 """DCache PortInterface Test
   2     starting as a copy to test_ldst_pi.py
   3 """
   4
   5 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   6 from nmigen.cli import main
   7 from nmigen.cli import rtlil
   8 from nmutil.mask import Mask, masked
   9 from nmutil.util import Display
  10 from random import randint, seed
  11 from nmigen.sim import Simulator, Delay, Settle
  12 from nmutil.util import wrap
  13
  14 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  15 from soc.config.test.test_loadstore import TestMemPspec
  16 from soc.config.loadstore import ConfigMemoryPortInterface
  17
  18 from soc.fu.ldst.loadstore import LoadStore1
  19 from soc.experiment.mmu import MMU
  20 from soc.experiment.test import pagetables
  21
  22 from nmigen.compat.sim import run_simulation
  23
  24
  25
  26 stop = False
  27
  28 def wb_get(wb, mem):
  29     """simulator process for getting memory load requests
  30     """
  31
  32     global stop
  33     assert(stop==False)
  34
  35     while not stop:
  36         while True: # wait for dc_valid
  37             if stop:
  38                 return
  39             cyc = yield (wb.cyc)
  40             stb = yield (wb.stb)
  41             if cyc and stb:
  42                 break
  43             yield
  44         addr = (yield wb.adr) << 3
  45         if addr not in mem:
  46             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  47
  48         # read or write?
  49         we = (yield wb.we)
  50         if we:
  51             store = (yield wb.dat_w)
  52             sel = (yield wb.sel)
  53             data = mem.get(addr, 0)
  54             # note we assume 8-bit sel, here
  55             res = 0
  56             for i in range(8):
  57                 mask = 0xff << (i*8)
  58                 if sel & (1<<i):
  59                     res |= store & mask
  60                 else:
  61                     res |= data & mask
  62             mem[addr] = res
  63             print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
  64         else:
  65             data = mem.get(addr, 0)
  66             yield wb.dat_r.eq(data)
  67             print ("    DCACHE get %x data %x" % (addr, data))
  68
  69         yield wb.ack.eq(1)
  70         yield
  71         yield wb.ack.eq(0)
  72         yield
  73
  74 def setup_mmu():
  75
  76     global stop
  77     stop = False
  78
  79     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  80                          imem_ifacetype='',
  81                          addr_wid=48,
  82                          #disable_cache=True, # hmmm...
  83                          mask_wid=8,
  84                          reg_wid=64)
  85
  86     m = Module()
  87     comb = m.d.comb
  88     cmpi = ConfigMemoryPortInterface(pspec)
  89     m.submodules.ldst = ldst = cmpi.pi
  90     m.submodules.mmu = mmu = MMU()
  91     dcache = ldst.dcache
  92
  93     l_in, l_out = mmu.l_in, mmu.l_out
  94     d_in, d_out = dcache.d_in, dcache.d_out
  95     wb_out, wb_in = dcache.wb_out, dcache.wb_in
  96
  97     # link mmu and dcache together
  98     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  99     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 100
 101     # link ldst and MMU together
 102     comb += l_in.eq(ldst.m_out)
 103     comb += ldst.m_in.eq(l_out)
 104
 105     return m, cmpi
 106
 107 ### test case for dcbz
 108
 109 def _test_dcbz_addr_100e0(dut, mem):
 110     mmu = dut.submodules.mmu
 111     pi = dut.submodules.ldst.pi
 112     global stop
 113     stop = False
 114
 115     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 116     yield
 117
 118     addr = 0x100e0
 119     data = 0xf553b658ba7e1f51
 120
 121     yield from pi_st(pi, addr, data, 8, msr_pr=0)
 122     yield
 123
 124     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 125     assert ld_data == 0xf553b658ba7e1f51
 126     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 127     assert ld_data == 0xf553b658ba7e1f51
 128
 129     print("do_dcbz ===============")
 130     yield from pi_st(pi, addr, data, 8, msr_pr=0, is_dcbz=1)
 131     print("done_dcbz ===============")
 132     yield
 133
 134     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 135     print("ld_data after dcbz")
 136     print(ld_data)
 137     assert ld_data == 0
 138
 139     yield
 140     stop = True
 141
 142 def test_dcbz_addr_100e0():
 143
 144     m, cmpi = setup_mmu()
 145
 146     mem = pagetables.test1
 147
 148     # nmigen Simulation
 149     sim = Simulator(m)
 150     sim.add_clock(1e-6)
 151
 152     sim.add_sync_process(wrap(_test_dcbz_addr_100e0(m, mem)))
 153     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 154     with sim.write_vcd('test_dcbz_addr_zero.vcd'):
 155         sim.run()
 156
 157 if __name__ == '__main__':
 158     test_dcbz_addr_100e0()