1 from nmigen
import Signal
, Const
2 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
3 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
4 from soc
.fu
.pipe_data
import IntegerData
5 from ieee754
.fpcommon
.getop
import FPPipeContext
6 from soc
.decoder
.power_decoder2
import Data
9 class ALUInputData(IntegerData
):
10 regspec
= [('INT', 'a', '0:63'),
12 ('XER', 'xer_so', '32'),
13 ('XER', 'xer_ca', '34,45')]
14 def __init__(self
, pspec
):
15 super().__init
__(pspec
)
16 self
.a
= Signal(64, reset_less
=True) # RA
17 self
.b
= Signal(64, reset_less
=True) # RB/immediate
18 self
.xer_so
= Signal(reset_less
=True) # XER bit 32: SO
19 self
.xer_ca
= Signal(2, reset_less
=True) # XER bit 34/45: CA/CA32
22 yield from super().__iter
__()
30 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
31 self
.xer_ca
.eq(i
.xer_ca
),
32 self
.xer_so
.eq(i
.xer_so
)]
35 class ALUOutputData(IntegerData
):
36 regspec
= [('INT', 'o', '0:63'),
38 ('XER', 'xer_ca', '34,45'),
39 ('XER', 'xer_ov', '33,44'),
40 ('XER', 'xer_so', '32')]
41 def __init__(self
, pspec
):
42 super().__init
__(pspec
)
43 self
.o
= Signal(64, reset_less
=True, name
="stage_o")
44 self
.cr0
= Data(4, name
="cr0")
45 self
.xer_ca
= Data(2, name
="xer_co") # bit0: ca, bit1: ca32
46 self
.xer_ov
= Data(2, name
="xer_ov") # bit0: ov, bit1: ov32
47 self
.xer_so
= Data(1, name
="xer_so")
50 yield from super().__iter
__()
59 return lst
+ [self
.o
.eq(i
.o
),
60 self
.xer_ca
.eq(i
.xer_ca
),
62 self
.xer_ov
.eq(i
.xer_ov
), self
.xer_so
.eq(i
.xer_so
)]
66 regspec
= (ALUInputData
.regspec
, ALUOutputData
.regspec
)
67 opsubsetkls
= CompALUOpSubset
68 def __init__(self
, id_wid
, op_wid
):
69 self
.pipekls
= SimpleHandshakeRedir
72 self
.opkls
= lambda _
: self
.opsubsetkls(name
="op")