src/soc/fu/div/pipe_data.py

   1 from nmigen import Signal, Const
   2 from soc.fu.pipe_data import IntegerData
   3 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   4 from soc.fu.alu.pipe_data import ALUInputData  # TODO: check this
   5 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   6 from ieee754.div_rem_sqrt_rsqrt.core import (
   7     DivPipeCoreConfig, DivPipeCoreInputData,
   8     DivPipeCoreInterstageData, DivPipeCoreOutputData)
   9
  10
  11 class DivPipeSpec(CommonPipeSpec):
  12     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
  13     opsubsetkls = CompLogicalOpSubset
  14     core_config = DivPipeCoreConfig(
  15         bit_width=64,
  16         fract_width=64,
  17         log2_radix=3,
  18     )
  19
  20
  21 class CoreBaseData(ALUInputData):
  22     def __init__(self, pspec, core_data_class):
  23         super().__init__(pspec)
  24         self.core = core_data_class(pspec.core_config)
  25         self.divisor_neg = Signal(1, reset_less=True)
  26         self.dividend_neg = Signal(1, reset_less=True)
  27
  28     def __iter__(self):
  29         yield from super().__iter__()
  30         yield from self.core.__iter__(self)
  31         yield self.divisor_neg
  32         yield self.dividend_neg
  33
  34     def eq(self, rhs):
  35         return super().eq(rhs) + \
  36             self.core.eq(rhs.core) + \
  37             [self.divisor_neg.eq(rhs.divisor_neg),
  38              self.dividend_neg.eq(rhs.dividend_neg)]
  39
  40
  41 class CoreInputData(CoreBaseData):
  42     def __init__(self, pspec):
  43         super().__init__(pspec, DivPipeCoreInputData)
  44
  45
  46 class CoreInterstageData(CoreBaseData):
  47     def __init__(self, pspec):
  48         super().__init__(pspec, DivPipeCoreInterstageData)
  49
  50
  51 class CoreOutputData(CoreBaseData):
  52     def __init__(self, pspec):
  53         super().__init__(pspec, DivPipeCoreOutputData)