804643df5a01160c6996bae3fe7d8c89133ecf16
1 # Proof of correctness for partitioned equal signal combiner
2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
4 from nmigen
import (Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
,
6 from nmigen
.asserts
import Assert
, AnyConst
, Assume
, Cover
7 from nmigen
.test
.utils
import FHDLTestCase
8 from nmigen
.cli
import rtlil
10 from soc
.fu
.logical
.main_stage
import LogicalMainStage
11 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
12 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
13 from soc
.decoder
.power_enums
import InternalOp
17 # This defines a module to drive the device under test and assert
18 # properties about its outputs
19 class Driver(Elaboratable
):
24 def elaborate(self
, platform
):
28 rec
= CompALUOpSubset()
30 # Setup random inputs for dut.op
34 comb
+= p
.eq(AnyConst(width
))
36 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=recwidth
)
37 m
.submodules
.dut
= dut
= LogicalMainStage(pspec
)
39 # convenience variables
42 carry_in
= dut
.i
.carry_in
44 carry_out
= dut
.o
.carry_out
48 comb
+= [a
.eq(AnyConst(64)),
50 carry_in
.eq(AnyConst(1)),
51 so_in
.eq(AnyConst(1))]
53 comb
+= dut
.i
.ctx
.op
.eq(rec
)
55 # Assert that op gets copied from the input to output
56 for rec_sig
in rec
.ports():
58 dut_sig
= getattr(dut
.o
.ctx
.op
, name
)
59 comb
+= Assert(dut_sig
== rec_sig
)
61 # signed and signed/32 versions of input a
62 a_signed
= Signal(signed(64))
63 a_signed_32
= Signal(signed(32))
64 comb
+= a_signed
.eq(a
)
65 comb
+= a_signed_32
.eq(a
[0:32])
67 # main assertion of arithmetic operations
68 with m
.Switch(rec
.insn_type
):
69 with m
.Case(InternalOp
.OP_AND
):
70 comb
+= Assert(dut
.o
.o
== a
& b
)
71 with m
.Case(InternalOp
.OP_OR
):
72 comb
+= Assert(dut
.o
.o
== a | b
)
73 with m
.Case(InternalOp
.OP_XOR
):
74 comb
+= Assert(dut
.o
.o
== a ^ b
)
79 class LogicalTestCase(FHDLTestCase
):
80 def test_formal(self
):
82 self
.assertFormal(module
, mode
="bmc", depth
=2)
83 self
.assertFormal(module
, mode
="cover", depth
=2)
86 vl
= rtlil
.convert(dut
, ports
=[])
87 with
open("main_stage.il", "w") as f
:
91 if __name__
== '__main__':